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[/] [i2s_to_wb/] [trunk/] [sim/] [src/] [tb_reset.v] - Blame information for rev 2

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1 2 qaztronic
// --------------------------------------------------------------------
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//
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// --------------------------------------------------------------------
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`timescale 1ns/10ps
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module
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  tb_reset
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  #(
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    parameter ASSERT_TIME = 32
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  )
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  (
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    output        rst_out
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  );
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  reg tb_rst;
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  initial
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      tb_rst <= 1'b1;
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  task assert_reset;
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    begin
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    tb_rst = 1'b1;
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    #ASSERT_TIME;
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    tb_rst = 1'b0;
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    $display( "-#- %15.t | %m: tb_rst asserted!", $time );
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    end
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  endtask
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  assign rst_out = tb_rst;
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endmodule
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