URL https://opencores.org/ocsvn/i2s_to_wb/i2s_to_wb/trunk

Subversion Repositories i2s_to_wb

[/] [i2s_to_wb/] [trunk/] [sim/] [tests/] [debug/] [the_test.v] - Blame information for rev 2

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// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module the_test(
                input tb_clk,
                input tb_rst
              );
 
  reg [31:0] d_out;
 
  task run_the_test;
    begin
 
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
 
      repeat(6) @(posedge tb_clk);
 
//       wbm.wb_write(0, 0, 32'h6000_0004, 32'habba_beef);
//       wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001); 
//       wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000); 
//       repeat(2) @(posedge tb_clk); 
//       
//       wbm.wb_write(0, 0, 32'h6000_0004, 32'hcafe_1a7a);
//       wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001); 
//       wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000); 
//       repeat(2) @(posedge tb_clk); 
//       
//       wbm.wb_write(0, 0, 32'h6000_0004, 32'h3333_3333);
//       wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001); 
//       wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000); 
//       repeat(2) @(posedge tb_clk); 
//       
//       
//       wbm.wb_write(0, 0, 32'h6000_0004, 32'hffff_ffff);
//       wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001); 
//       wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000); 
//       repeat(2) @(posedge tb_clk); 
 
      wbm.wb_write(0, 0, 32'h6000_0010, 32'h8001_0000);
      repeat(2) @(posedge tb_clk);
 
      // enable i2s
      repeat(2) @(posedge tb_clk);
      rx_bfm.enable_bfm();
 
      repeat(2) @(posedge tb_clk);
      wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001);
 
//       repeat(6*32) @(posedge tb_clk); 
 
 
      repeat('h72) @(posedge i_i2s_to_wb_top.i2s_ws_i);
 
 
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
 
   end
  endtask
 
 
endmodule
 

Line No.	Rev	Author	Line
1	2	qaztronic	`// --------------------------------------------------------------------`
2			`//`
3			`// --------------------------------------------------------------------`
4
5			`timescale 1ns/10ps
6
7
8			`module the_test(`
9			`input tb_clk,`
10			`input tb_rst`
11			`);`
12
13			`reg [31:0] d_out;`
14
15			`task run_the_test;`
16			`begin`
17
18			`// --------------------------------------------------------------------`
19			`// insert test below`
20			`// --------------------------------------------------------------------`
21
22			`repeat(6) @(posedge tb_clk);`
23
24			`// wbm.wb_write(0, 0, 32'h6000_0004, 32'habba_beef);`
25			`// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001);`
26			`// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000);`
27			`// repeat(2) @(posedge tb_clk);`
28			`//`
29			`// wbm.wb_write(0, 0, 32'h6000_0004, 32'hcafe_1a7a);`
30			`// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001);`
31			`// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000);`
32			`// repeat(2) @(posedge tb_clk);`
33			`//`
34			`// wbm.wb_write(0, 0, 32'h6000_0004, 32'h3333_3333);`
35			`// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001);`
36			`// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000);`
37			`// repeat(2) @(posedge tb_clk);`
38			`//`
39			`//`
40			`// wbm.wb_write(0, 0, 32'h6000_0004, 32'hffff_ffff);`
41			`// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001);`
42			`// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000);`
43			`// repeat(2) @(posedge tb_clk);`
44
45			`wbm.wb_write(0, 0, 32'h6000_0010, 32'h8001_0000);`
46			`repeat(2) @(posedge tb_clk);`
47
48			`// enable i2s`
49			`repeat(2) @(posedge tb_clk);`
50			`rx_bfm.enable_bfm();`
51
52			`repeat(2) @(posedge tb_clk);`
53			`wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001);`
54
55			`// repeat(6*32) @(posedge tb_clk);`
56
57
58			`repeat('h72) @(posedge i_i2s_to_wb_top.i2s_ws_i);`
59
60
61			`// --------------------------------------------------------------------`
62			`// insert test above`
63			`// --------------------------------------------------------------------`
64
65			`end`
66			`endtask`
67
68
69			`endmodule`
70

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Subversion Repositories i2s_to_wb

[/] [i2s_to_wb/] [trunk/] [sim/] [tests/] [debug/] [the_test.v] - Blame information for rev 2