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[/] [i2s_to_wb/] [trunk/] [src/] [i2s_to_wb_dma_fsm.v] - Blame information for rev 2

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//
//
//
 
`include "timescale.v"
 
 
module
  i2s_to_wb_dma_fsm
  (
    input           dma_enable,
    input           dma_ack_i,
 
    input           fifo_empty,
    input           fifo_full,
 
    output          fifo_wr_enable,
 
    output          dma_fsm_error,
 
    input           dma_clk_i,
    input           dma_rst_i
  );
 
 
  // -----------------------------
  //  state machine binary definitions
  parameter IDLE_STATE  = 4'b0001;
  parameter DMA_STATE   = 4'b0010;
  parameter WAIT_STATE  = 4'b0100;
  parameter ERROR_STATE = 4'b1000;
 
 
  // -----------------------------
  //  state machine flop
  reg [3:0] state;
  reg [3:0] next_state;
 
  always @(posedge dma_clk_i)
    if(dma_rst_i)
      state <= IDLE_STATE;
    else
      state <= next_state;
 
 
  // -----------------------------
  //  state machine
  always @(*)
    case(state)
      IDLE_STATE:   if( dma_enable & fifo_empty )
                      next_state <= DMA_STATE;
                    else
                      next_state <= IDLE_STATE;
 
      DMA_STATE:    if( ~dma_enable | fifo_full )
                      next_state <= IDLE_STATE;
                    else if( ~dma_ack_i )
                      next_state <= WAIT_STATE;
                    else
                      next_state <= DMA_STATE;
 
      WAIT_STATE:   if( dma_ack_i )
                      next_state <= DMA_STATE;
                    else
                      next_state <= WAIT_STATE;
 
      ERROR_STATE:  next_state <= IDLE_STATE;
 
      default:      next_state <= ERROR_STATE;
 
    endcase
 
 
  // -----------------------------
  //  outputs
  assign fifo_wr_enable = ( (state == DMA_STATE) | (state == WAIT_STATE) ) & (next_state != WAIT_STATE) & dma_enable & ~fifo_full;
  assign dma_fsm_error  = (state == ERROR_STATE);
 
 
endmodule
 

Line No.	Rev	Author	Line
1	2	qaztronic	`//`
2			`//`
3			`//`
4
5			`include "timescale.v"
6
7
8			`module`
9			`i2s_to_wb_dma_fsm`
10			`(`
11			`input dma_enable,`
12			`input dma_ack_i,`
13
14			`input fifo_empty,`
15			`input fifo_full,`
16
17			`output fifo_wr_enable,`
18
19			`output dma_fsm_error,`
20
21			`input dma_clk_i,`
22			`input dma_rst_i`
23			`);`
24
25
26			`// -----------------------------`
27			`// state machine binary definitions`
28			`parameter IDLE_STATE = 4'b0001;`
29			`parameter DMA_STATE = 4'b0010;`
30			`parameter WAIT_STATE = 4'b0100;`
31			`parameter ERROR_STATE = 4'b1000;`
32
33
34			`// -----------------------------`
35			`// state machine flop`
36			`reg [3:0] state;`
37			`reg [3:0] next_state;`
38
39			`always @(posedge dma_clk_i)`
40			`if(dma_rst_i)`
41			`state <= IDLE_STATE;`
42			`else`
43			`state <= next_state;`
44
45
46			`// -----------------------------`
47			`// state machine`
48			`always @(*)`
49			`case(state)`
50			`IDLE_STATE: if( dma_enable & fifo_empty )`
51			`next_state <= DMA_STATE;`
52			`else`
53			`next_state <= IDLE_STATE;`
54
55			`DMA_STATE: if( ~dma_enable \| fifo_full )`
56			`next_state <= IDLE_STATE;`
57			`else if( ~dma_ack_i )`
58			`next_state <= WAIT_STATE;`
59			`else`
60			`next_state <= DMA_STATE;`
61
62			`WAIT_STATE: if( dma_ack_i )`
63			`next_state <= DMA_STATE;`
64			`else`
65			`next_state <= WAIT_STATE;`
66
67			`ERROR_STATE: next_state <= IDLE_STATE;`
68
69			`default: next_state <= ERROR_STATE;`
70
71			`endcase`
72
73
74			`// -----------------------------`
75			`// outputs`
76			`assign fifo_wr_enable = ( (state == DMA_STATE) \| (state == WAIT_STATE) ) & (next_state != WAIT_STATE) & dma_enable & ~fifo_full;`
77			`assign dma_fsm_error = (state == ERROR_STATE);`
78
79
80			`endmodule`
81

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[/] [i2s_to_wb/] [trunk/] [src/] [i2s_to_wb_dma_fsm.v] - Blame information for rev 2