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eightycc |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: Digit time pulse generator. Emits a pulse lasting 1 digit time
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// beginning at the first rising clk edge at/after in_pulse becomes true,
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// approximating rising-edge triggering by in_pulse.
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//
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// Additional Comments: Input init_history is a 0 for rising egde tiggering.
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// For falling edge triggering, set in_pulse to the complement of the signal
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// and set init_history to 1.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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module digit_pulse (
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input rst, clk,
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input in_pulse,
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input init_history,
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output reg out_pulse
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);
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reg history;
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always @(posedge clk) begin
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if (rst) begin
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out_pulse <= 0;
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history <= init_history;
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end else if (out_pulse) begin
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out_pulse <= 0;
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end else if (in_pulse) begin
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out_pulse <= ~history;
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history <= 1;
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end else begin
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history <= 0;
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end
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end;
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endmodule
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