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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    23:02:15 11/13/2009 
// Design Name: 
// Module Name:    iotools 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module porta(dataout, datain, mode, extinout);
        output [7:0] dataout;
        input [7:0] datain;
        input mode;
        inout [7:0] extinout;
        assign dataout=(mode==1)?extinout:8'bz; //input to i8255
        assign extinout=(mode==0)?datain:8'bz; //output
endmodule
module portb(dataout, datain, mode, extinout);
        output [7:0] dataout;
        input [7:0] datain;
        input mode;
        inout [7:0] extinout;
        assign dataout=(mode==1)?extinout:8'bz;
        assign extinout=(mode==0)?datain:8'bz;
endmodule
module portc(dataout, datain, mode, extinout);
        output [3:0] dataout;
        input [3:0] datain;
        input [3:0] mode;
        inout [3:0] extinout;
        assign dataout[0:0]=(mode[0:0])?extinout[0:0]:1'bz;
        assign dataout[1:1]=(mode[1:1])?extinout[1:1]:1'bz;
        assign dataout[2:2]=(mode[2:2])?extinout[2:2]:1'bz;
        assign dataout[3:3]=(mode[3:3])?extinout[3:3]:1'bz;
        assign extinout[0:0]=(mode[0:0])?1'bz:datain[0:0];
        assign extinout[1:1]=(mode[1:1])?1'bz:datain[1:1];
        assign extinout[2:2]=(mode[2:2])?1'bz:datain[2:2];
        assign extinout[3:3]=(mode[3:3])?1'bz:datain[3:3];
endmodule
 
module pactl(dataout, datain, portaio, portcio, signals, cw, sel);
        //Group A control
        output [7:0] dataout;
        output reg [3:0] signals;
        input [7:0] datain;
        inout [7:0] portaio; //external port
        inout [3:0] portcio; //-//-
        input [3:0] cw;      //control word
        input [1:0] sel;     //selection
        wire [7:0] portadatain;
        reg [7:0] portadataout;
        wire [3:0] portcdatain;
        reg [3:0] portcdataout;
        reg oflag; //control a input to i8255 core
        reg ocflag; //control c input
        reg [7:0] buffer; //internal latch
        reg [3:0] cbuffer; //internal latch for port c
        reg [3:0] pccw; //control each of 4 wires of port c
        reg pacw;       //0-output, 1 -input
        reg [3:0] pcio;
        reg bitctl;
        reg [1:0] intmode; //mode:0-normal, 1- strob, 2-extra
        reg awflag; //external output enabled
        reg cwflag; //-//-
        porta pa1(.dataout(portadatain), .datain(portadataout), .mode(pacw), .extinout(portaio));
        portc pch(.dataout(portcdatain), .datain(portcdataout), .mode(pccw), .extinout(portcio));
        //read data to internal bus supports latches
        assign dataout=(oflag)?(intmode==0)?portadatain:
                buffer:(ocflag)?(intmode==0)?{portcdatain, 4'bz}:
                {cbuffer, 4'bz}:8'bz;
        //assign portadata=(awflag)?buffer:8'bz; //send data to porta
        //assign portcdata=(cwflag)?cbuffer:4'bz;//send data to hight 4 bits of port c
        always @(negedge sel[0:0]) begin
                oflag<=0;
                ocflag<=0;
        end
        always @(posedge sel[0:0]) begin
                case (cw)
                        4'h1: begin //write cw
                                oflag=0;
                                ocflag=0;
                                awflag=0;
                                cwflag=0;
                                //wait_data();
                                if (datain[7:7]==0) begin
                                        //set bits in port c
                                        if (datain[0:0]) bitctl=1;
                                        else bitctl=0;
                                        case(datain[3:1])
                                                3'b000: pcio[0:0]=bitctl;
                                                3'b001: pcio[1:1]=bitctl;
                                                3'b010: pcio[2:2]=bitctl;
                                                3'b011: pcio[3:3]=bitctl;
                                                default: pcio=0;
                                        endcase
                                end
                                else begin
                                        //setup group
                                        case (datain[6:5])
                                                2'b00: begin
                                                        //simple io mode
                                                        intmode=0; //no latched input
                                                        pacw=datain[4:4];
                                                        awflag=~pacw;
                                                        if (pacw==0) portadataout=0;
                                                        if (datain[3:3]==0) begin
                                                                pccw=0;
                                                                portcdataout=0;
                                                                end
                                                        else begin
                                                                pccw=4'b1111;
                                                        end
                                                        cwflag=~datain[3:3];
                                                        end
                                                2'b01: begin
                                                        intmode=1;
                                                        pccw[0:0]=0;//intrb-->
                                                        pccw[1:1]=0;//ibfb-->
                                                        pccw[2:2]=1;//nSTBB<--
                                                        pccw[3:3]=0;//no val
                                                        end
                                                2'b10: intmode=2;
                                                default: intmode=2;
                                         endcase
                                         end
                                        end
                                4'h2: begin //write port a
                                        portadataout=datain;
                                        oflag=0;
                                        ocflag=0;
                                        awflag=1;
                                        end
                                4'h3: begin //read port a
                                        if (intmode!=0) buffer=portadatain;
                                        awflag=0;
                                        oflag=1;
                                        end
                                4'h4: begin //write port c
                                        portcdataout=datain[7:4];
                                        oflag=0;
                                        ocflag=0;
                                        cwflag=1;
                                        end
                                4'h5: begin //read port c
                                        if(intmode!=0) cbuffer=portcdatain;
                                        cwflag=0;
                                        oflag=0;
                                        ocflag=1;
                                        end
                                endcase
                        end
endmodule
 
module pbctl(dataout, datain, portbio, portcio, signals, cw, sel);
        //Group B control
        output [7:0] dataout;
        output reg [3:0] signals;
        input [7:0] datain;
        inout [7:0] portbio; //external port
        inout [3:0] portcio; //-//-
        input [3:0] cw;      //control word
        input [1:0] sel;     //selection
        wire [7:0] portbdatain;
        reg [7:0] portbdataout;
        wire [3:0] portcdatain;
        reg [3:0] portcdataout;
        reg oflag; //control a input to i8255 core
        reg ocflag; //control c input
        reg [7:0] buffer; //internal latch
        reg [3:0] cbuffer; //internal latch for port c
        reg [3:0] pccw; //control each of 4 wires of port c
        reg pbcw;       //0-output, 1 -input
        reg [3:0] pcio;
        reg bitctl;
        reg [1:0] intmode; //mode:0-normal, 1- strob, 2-extra
        reg bwflag; //external output enabled
        reg cwflag; //-//-
        porta pb1(.dataout(portbdatain), .datain(portbdataout), .mode(pbcw), .extinout(portbio));
        portc pcl(.dataout(portcdatain), .datain(portcdataout), .mode(pccw), .extinout(portcio));
        //read data to internal bus supports latches
        assign dataout=(oflag)?(intmode==0)?portbdatain:
                buffer:(ocflag)?(intmode==0)?{4'bz, portcdatain}:
                {4'bz, cbuffer}:8'bz;
        //assign portbdata=(bwflag)?buffer:8'bz; //send data to porta
        //assign portcdata=(cwflag)?cbuffer:4'bz;//send data to hight 4 bits of port c
        always @(negedge sel[1:1]) begin
                oflag<=0;
                ocflag<=0;
        end
        always @(posedge sel[1:1]) begin
                case (cw)
                        4'h1: begin //write cw
                                oflag=0;
                                ocflag=0;
                                bwflag=0;
                                cwflag=0;
                                if (datain[7:7]==0) begin
                                        //set bits in port c
                                        if (datain[0:0]) bitctl=1;
                                        else bitctl=0;
                                        case(datain[3:1])
                                                3'b100: pcio[0:0]=bitctl;
                                                3'b101: pcio[1:1]=bitctl;
                                                3'b110: pcio[2:2]=bitctl;
                                                3'b111: pcio[3:3]=bitctl;
                                                default: pcio=0;
                                        endcase
                                end
                                else begin
                                        //setup group
                                        case (datain[2:2])
                                                1'b0: begin
                                                        //simple io mode
                                                        intmode=0; //no latched input
                                                        pbcw=datain[1:1];
                                                        bwflag=~pbcw;
                                                        if (pbcw==0) portbdataout=0;
                                                        if (datain[0:0]==0) begin
                                                                pccw=0;
                                                                portcdataout=0;
                                                                end
                                                        else begin
                                                                pccw=4'b1111;
                                                        end
                                                        cwflag=~datain[0:0];
                                                        end
                                                1'b01: begin
                                                        intmode=1;
                                                        pccw[0:0]=0;//intrb-->
                                                        pccw[1:1]=0;//ibfb-->
                                                        pccw[2:2]=1;//nSTBB<--
                                                        pccw[3:3]=0;//no val
                                                        end
                                                default: intmode=1;
                                         endcase
                                         end
                                        end
                                4'h2: begin //write port a
                                        portbdataout=datain;
                                        oflag=0;
                                        ocflag=0;
                                        bwflag=1;
                                        end
                                4'h3: begin //read port a
                                        if (intmode!=0) buffer=portbdatain;
                                        bwflag=0;
                                        oflag=1;
                                        end
                                4'h4: begin //write port c
                                        portcdataout=datain[3:0];
                                        oflag=0;
                                        ocflag=0;
                                        cwflag=1;
                                        end
                                4'h5: begin //read port c
                                        if(intmode!=0) cbuffer=portcdatain;
                                        cwflag=0;
                                        oflag=0;
                                        ocflag=1;
                                        end
                                endcase
                        end
endmodule
 
module i8255(data, reset, ncs, nrd, nwr, addr, pa, pb, pch, pcl);
        //main trigger events is nrd and nwr
        //after all operation this ones must be set to 1 both
        //ncs - selects device
        //WARNING:
        //you must setup 'data' bus first before sending nWR
        //because iSIM has issue with inout assignment delay 
        inout [7:0] data; //data to/from chip
        input reset;
        input ncs; //inverted CS
        input nrd; //inverted RD
        input nwr; //inverted WR
        input [1:0] addr; //2 bits addr(A0,A1)
        inout [7:0] pa;   //port a
        inout [7:0] pb;   //port b
        inout [3:0] pch;  //port c hight 4 bits
        inout [3:0] pcl;  //port c low 4 bits
        reg [1:0] firststep;
        reg [2:0] nextstep;
        reg [7:0] mode;
        wire [7:0] bufferin;
        reg [7:0] bufferout;
        reg [7:0] intdata;
        reg iflag; //move to 'data'
        reg oflag; //output to 'buffer'
        reg extrai;
        reg extrao;
        reg [1:0] sel;
        //wire [7:0] odata;
        //group A
        wire [3:0] grasigs;
        reg [3:0] gracw;
        //group B
        wire [3:0] grbsigs;
        reg [3:0] grbcw;
        assign data=(iflag)?bufferin:(extrai)?intdata:8'bz;
        pactl grpa(.dataout(bufferin), .datain(bufferout), .portaio(pa), .portcio(pch),
                .signals(grasigs), .cw(gracw), .sel(sel));
        pbctl grpb(.dataout(bufferin), .datain(bufferout), .portbio(pb), .portcio(pcl),
                .signals(grbsigs), .cw(grbcw), .sel(sel));
        always @(posedge reset) begin
                                oflag<=0;
                                extrao<=1;
                                mode<=8'h9b;
                                firststep<=0;
                                nextstep<=0;
                                iflag<=0;
                                extrai<=0;
                                intdata<=8'h9b;
                                gracw<=1;//init group A
                                grbcw<=1;//init group B
                                bufferout=8'h9b;
                                sel<=3;
                                end
        always @(negedge reset) begin
                sel<=0;
                extrai<=0;
                extrao<=0;
                gracw<=0;
                grbcw<=0;
                end
        always @(negedge nwr) begin
                //write event
                if(ncs==0) begin
                        case(addr)
                                //control register
                                2'b11: begin //write - control
                                        if (data[7:7]==0) begin
                                                gracw<=1;
                                        end
                                        else begin
                                                //send mode to the all groups
                                                iflag<=0;
                                                extrai<=0;
                                                oflag<=0;
                                                mode<=data;
                                                intdata<=data;
                                                bufferout<=data;
                                                gracw<=1;
                                                grbcw<=1;
                                                sel<=3;
                                        end
                                        end
                                2'b00: begin//write - porta
                                        $display("Value: %b", data);
                                        oflag<=1;
                                        gracw<=2;
                                        bufferout<=data;
                                        sel<=3;
                                        end
                                2'b01: begin //write - portb
                                        oflag<=1;
                                        grbcw<=2;
                                        bufferout<=data;
                                        sel<=3;
                                        end
                                2'b10: begin//write - portc
                                        oflag<=1;
                                        gracw<=4;
                                        grbcw<=4;
                                        bufferout<=data;
                                        sel<=3;
                                        end
                         endcase
                        end
        end
        always @(posedge nwr) begin
                //write completed event
                if(ncs==0) begin
                        extrao<=0;
                        extrai<=0;
                        firststep<=0;
                        nextstep<=0;
                        iflag<=0;
                        oflag<=0;
                        gracw<=0;
                        grbcw<=0;
                        sel<=0;
                end
        end
        always @(negedge nrd) begin
                //read event
                if(ncs==0) begin
                        case (addr)
                                2'b11: begin//read - control
                                        intdata<=mode;
                                        iflag<=0;
                                        oflag<=0;
                                        extrai<=1;
                                        end
                                2'b00: begin //read - porta
                                        iflag<=1;
                                        gracw<=3;
                                        sel<=1;
                                        end
                                2'b01: begin//read - portb
                                        iflag<=1;
                                        grbcw<=3;
                                        sel<=1;
                                        end
                                2'b10: begin//read - portc
                                        iflag<=1;
                                        gracw<=5;
                                        grbcw<=5;
                                        sel<=3;
                                        end
                         endcase
                        end
        end
        always @(posedge nrd) begin
                //read completed event
                if(ncs==0) begin
                        extrao<=0;
                        extrai<=0;
                        firststep<=0;
                        nextstep<=0;
                        iflag<=0;
                        oflag<=0;
                        gracw<=0;
                        grbcw<=0;
                        sel<=0;
                end
        end
endmodule

Line No.	Rev	Author	Line
1	2	Malasar	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 23:02:15 11/13/2009`
7			`// Design Name:`
8			`// Module Name: iotools`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`module porta(dataout, datain, mode, extinout);`
22			`output [7:0] dataout;`
23			`input [7:0] datain;`
24			`input mode;`
25			`inout [7:0] extinout;`
26			`assign dataout=(mode==1)?extinout:8'bz; //input to i8255`
27			`assign extinout=(mode==0)?datain:8'bz; //output`
28			`endmodule`
29			`module portb(dataout, datain, mode, extinout);`
30			`output [7:0] dataout;`
31			`input [7:0] datain;`
32			`input mode;`
33			`inout [7:0] extinout;`
34			`assign dataout=(mode==1)?extinout:8'bz;`
35			`assign extinout=(mode==0)?datain:8'bz;`
36			`endmodule`
37			`module portc(dataout, datain, mode, extinout);`
38			`output [3:0] dataout;`
39			`input [3:0] datain;`
40			`input [3:0] mode;`
41			`inout [3:0] extinout;`
42			`assign dataout[0:0]=(mode[0:0])?extinout[0:0]:1'bz;`
43			`assign dataout[1:1]=(mode[1:1])?extinout[1:1]:1'bz;`
44			`assign dataout[2:2]=(mode[2:2])?extinout[2:2]:1'bz;`
45			`assign dataout[3:3]=(mode[3:3])?extinout[3:3]:1'bz;`
46			`assign extinout[0:0]=(mode[0:0])?1'bz:datain[0:0];`
47			`assign extinout[1:1]=(mode[1:1])?1'bz:datain[1:1];`
48			`assign extinout[2:2]=(mode[2:2])?1'bz:datain[2:2];`
49			`assign extinout[3:3]=(mode[3:3])?1'bz:datain[3:3];`
50			`endmodule`
51
52			`module pactl(dataout, datain, portaio, portcio, signals, cw, sel);`
53			`//Group A control`
54			`output [7:0] dataout;`
55			`output reg [3:0] signals;`
56			`input [7:0] datain;`
57			`inout [7:0] portaio; //external port`
58			`inout [3:0] portcio; //-//-`
59			`input [3:0] cw; //control word`
60			`input [1:0] sel; //selection`
61			`wire [7:0] portadatain;`
62			`reg [7:0] portadataout;`
63			`wire [3:0] portcdatain;`
64			`reg [3:0] portcdataout;`
65			`reg oflag; //control a input to i8255 core`
66			`reg ocflag; //control c input`
67			`reg [7:0] buffer; //internal latch`
68			`reg [3:0] cbuffer; //internal latch for port c`
69			`reg [3:0] pccw; //control each of 4 wires of port c`
70			`reg pacw; //0-output, 1 -input`
71			`reg [3:0] pcio;`
72			`reg bitctl;`
73			`reg [1:0] intmode; //mode:0-normal, 1- strob, 2-extra`
74			`reg awflag; //external output enabled`
75			`reg cwflag; //-//-`
76			`porta pa1(.dataout(portadatain), .datain(portadataout), .mode(pacw), .extinout(portaio));`
77			`portc pch(.dataout(portcdatain), .datain(portcdataout), .mode(pccw), .extinout(portcio));`
78			`//read data to internal bus supports latches`
79			`assign dataout=(oflag)?(intmode==0)?portadatain:`
80			`buffer:(ocflag)?(intmode==0)?{portcdatain, 4'bz}:`
81			`{cbuffer, 4'bz}:8'bz;`
82			`//assign portadata=(awflag)?buffer:8'bz; //send data to porta`
83			`//assign portcdata=(cwflag)?cbuffer:4'bz;//send data to hight 4 bits of port c`
84			`always @(negedge sel[0:0]) begin`
85			`oflag<=0;`
86			`ocflag<=0;`
87			`end`
88			`always @(posedge sel[0:0]) begin`
89			`case (cw)`
90			`4'h1: begin //write cw`
91			`oflag=0;`
92			`ocflag=0;`
93			`awflag=0;`
94			`cwflag=0;`
95			`//wait_data();`
96			`if (datain[7:7]==0) begin`
97			`//set bits in port c`
98			`if (datain[0:0]) bitctl=1;`
99			`else bitctl=0;`
100			`case(datain[3:1])`
101			`3'b000: pcio[0:0]=bitctl;`
102			`3'b001: pcio[1:1]=bitctl;`
103			`3'b010: pcio[2:2]=bitctl;`
104			`3'b011: pcio[3:3]=bitctl;`
105			`default: pcio=0;`
106			`endcase`
107			`end`
108			`else begin`
109			`//setup group`
110			`case (datain[6:5])`
111			`2'b00: begin`
112			`//simple io mode`
113			`intmode=0; //no latched input`
114			`pacw=datain[4:4];`
115			`awflag=~pacw;`
116			`if (pacw==0) portadataout=0;`
117			`if (datain[3:3]==0) begin`
118			`pccw=0;`
119			`portcdataout=0;`
120			`end`
121			`else begin`
122			`pccw=4'b1111;`
123			`end`
124			`cwflag=~datain[3:3];`
125			`end`
126			`2'b01: begin`
127			`intmode=1;`
128			`pccw[0:0]=0;//intrb-->`
129			`pccw[1:1]=0;//ibfb-->`
130			`pccw[2:2]=1;//nSTBB<--`
131			`pccw[3:3]=0;//no val`
132			`end`
133			`2'b10: intmode=2;`
134			`default: intmode=2;`
135			`endcase`
136			`end`
137			`end`
138			`4'h2: begin //write port a`
139			`portadataout=datain;`
140			`oflag=0;`
141			`ocflag=0;`
142			`awflag=1;`
143			`end`
144			`4'h3: begin //read port a`
145			`if (intmode!=0) buffer=portadatain;`
146			`awflag=0;`
147			`oflag=1;`
148			`end`
149			`4'h4: begin //write port c`
150			`portcdataout=datain[7:4];`
151			`oflag=0;`
152			`ocflag=0;`
153			`cwflag=1;`
154			`end`
155			`4'h5: begin //read port c`
156			`if(intmode!=0) cbuffer=portcdatain;`
157			`cwflag=0;`
158			`oflag=0;`
159			`ocflag=1;`
160			`end`
161			`endcase`
162			`end`
163			`endmodule`
164
165			`module pbctl(dataout, datain, portbio, portcio, signals, cw, sel);`
166			`//Group B control`
167			`output [7:0] dataout;`
168			`output reg [3:0] signals;`
169			`input [7:0] datain;`
170			`inout [7:0] portbio; //external port`
171			`inout [3:0] portcio; //-//-`
172			`input [3:0] cw; //control word`
173			`input [1:0] sel; //selection`
174			`wire [7:0] portbdatain;`
175			`reg [7:0] portbdataout;`
176			`wire [3:0] portcdatain;`
177			`reg [3:0] portcdataout;`
178			`reg oflag; //control a input to i8255 core`
179			`reg ocflag; //control c input`
180			`reg [7:0] buffer; //internal latch`
181			`reg [3:0] cbuffer; //internal latch for port c`
182			`reg [3:0] pccw; //control each of 4 wires of port c`
183			`reg pbcw; //0-output, 1 -input`
184			`reg [3:0] pcio;`
185			`reg bitctl;`
186			`reg [1:0] intmode; //mode:0-normal, 1- strob, 2-extra`
187			`reg bwflag; //external output enabled`
188			`reg cwflag; //-//-`
189			`porta pb1(.dataout(portbdatain), .datain(portbdataout), .mode(pbcw), .extinout(portbio));`
190			`portc pcl(.dataout(portcdatain), .datain(portcdataout), .mode(pccw), .extinout(portcio));`
191			`//read data to internal bus supports latches`
192			`assign dataout=(oflag)?(intmode==0)?portbdatain:`
193			`buffer:(ocflag)?(intmode==0)?{4'bz, portcdatain}:`
194			`{4'bz, cbuffer}:8'bz;`
195			`//assign portbdata=(bwflag)?buffer:8'bz; //send data to porta`
196			`//assign portcdata=(cwflag)?cbuffer:4'bz;//send data to hight 4 bits of port c`
197			`always @(negedge sel[1:1]) begin`
198			`oflag<=0;`
199			`ocflag<=0;`
200			`end`
201			`always @(posedge sel[1:1]) begin`
202			`case (cw)`
203			`4'h1: begin //write cw`
204			`oflag=0;`
205			`ocflag=0;`
206			`bwflag=0;`
207			`cwflag=0;`
208			`if (datain[7:7]==0) begin`
209			`//set bits in port c`
210			`if (datain[0:0]) bitctl=1;`
211			`else bitctl=0;`
212			`case(datain[3:1])`
213			`3'b100: pcio[0:0]=bitctl;`
214			`3'b101: pcio[1:1]=bitctl;`
215			`3'b110: pcio[2:2]=bitctl;`
216			`3'b111: pcio[3:3]=bitctl;`
217			`default: pcio=0;`
218			`endcase`
219			`end`
220			`else begin`
221			`//setup group`
222			`case (datain[2:2])`
223			`1'b0: begin`
224			`//simple io mode`
225			`intmode=0; //no latched input`
226			`pbcw=datain[1:1];`
227			`bwflag=~pbcw;`
228			`if (pbcw==0) portbdataout=0;`
229			`if (datain[0:0]==0) begin`
230			`pccw=0;`
231			`portcdataout=0;`
232			`end`
233			`else begin`
234			`pccw=4'b1111;`
235			`end`
236			`cwflag=~datain[0:0];`
237			`end`
238			`1'b01: begin`
239			`intmode=1;`
240			`pccw[0:0]=0;//intrb-->`
241			`pccw[1:1]=0;//ibfb-->`
242			`pccw[2:2]=1;//nSTBB<--`
243			`pccw[3:3]=0;//no val`
244			`end`
245			`default: intmode=1;`
246			`endcase`
247			`end`
248			`end`
249			`4'h2: begin //write port a`
250			`portbdataout=datain;`
251			`oflag=0;`
252			`ocflag=0;`
253			`bwflag=1;`
254			`end`
255			`4'h3: begin //read port a`
256			`if (intmode!=0) buffer=portbdatain;`
257			`bwflag=0;`
258			`oflag=1;`
259			`end`
260			`4'h4: begin //write port c`
261			`portcdataout=datain[3:0];`
262			`oflag=0;`
263			`ocflag=0;`
264			`cwflag=1;`
265			`end`
266			`4'h5: begin //read port c`
267			`if(intmode!=0) cbuffer=portcdatain;`
268			`cwflag=0;`
269			`oflag=0;`
270			`ocflag=1;`
271			`end`
272			`endcase`
273			`end`
274			`endmodule`
275
276			`module i8255(data, reset, ncs, nrd, nwr, addr, pa, pb, pch, pcl);`
277			`//main trigger events is nrd and nwr`
278			`//after all operation this ones must be set to 1 both`
279			`//ncs - selects device`
280			`//WARNING:`
281			`//you must setup 'data' bus first before sending nWR`
282			`//because iSIM has issue with inout assignment delay`
283			`inout [7:0] data; //data to/from chip`
284			`input reset;`
285			`input ncs; //inverted CS`
286			`input nrd; //inverted RD`
287			`input nwr; //inverted WR`
288			`input [1:0] addr; //2 bits addr(A0,A1)`
289			`inout [7:0] pa; //port a`
290			`inout [7:0] pb; //port b`
291			`inout [3:0] pch; //port c hight 4 bits`
292			`inout [3:0] pcl; //port c low 4 bits`
293			`reg [1:0] firststep;`
294			`reg [2:0] nextstep;`
295			`reg [7:0] mode;`
296			`wire [7:0] bufferin;`
297			`reg [7:0] bufferout;`
298			`reg [7:0] intdata;`
299			`reg iflag; //move to 'data'`
300			`reg oflag; //output to 'buffer'`
301			`reg extrai;`
302			`reg extrao;`
303			`reg [1:0] sel;`
304			`//wire [7:0] odata;`
305			`//group A`
306			`wire [3:0] grasigs;`
307			`reg [3:0] gracw;`
308			`//group B`
309			`wire [3:0] grbsigs;`
310			`reg [3:0] grbcw;`
311			`assign data=(iflag)?bufferin:(extrai)?intdata:8'bz;`
312			`pactl grpa(.dataout(bufferin), .datain(bufferout), .portaio(pa), .portcio(pch),`
313			`.signals(grasigs), .cw(gracw), .sel(sel));`
314			`pbctl grpb(.dataout(bufferin), .datain(bufferout), .portbio(pb), .portcio(pcl),`
315			`.signals(grbsigs), .cw(grbcw), .sel(sel));`
316			`always @(posedge reset) begin`
317			`oflag<=0;`
318			`extrao<=1;`
319			`mode<=8'h9b;`
320			`firststep<=0;`
321			`nextstep<=0;`
322			`iflag<=0;`
323			`extrai<=0;`
324			`intdata<=8'h9b;`
325			`gracw<=1;//init group A`
326			`grbcw<=1;//init group B`
327			`bufferout=8'h9b;`
328			`sel<=3;`
329			`end`
330			`always @(negedge reset) begin`
331			`sel<=0;`
332			`extrai<=0;`
333			`extrao<=0;`
334			`gracw<=0;`
335			`grbcw<=0;`
336			`end`
337			`always @(negedge nwr) begin`
338			`//write event`
339			`if(ncs==0) begin`
340			`case(addr)`
341			`//control register`
342			`2'b11: begin //write - control`
343			`if (data[7:7]==0) begin`
344	3	Malasar	`gracw<=1;`
345	2	Malasar	`end`
346			`else begin`
347			`//send mode to the all groups`
348			`iflag<=0;`
349			`extrai<=0;`
350			`oflag<=0;`
351			`mode<=data;`
352			`intdata<=data;`
353			`bufferout<=data;`
354			`gracw<=1;`
355			`grbcw<=1;`
356			`sel<=3;`
357			`end`
358			`end`
359			`2'b00: begin//write - porta`
360			`$display("Value: %b", data);`
361			`oflag<=1;`
362			`gracw<=2;`
363			`bufferout<=data;`
364			`sel<=3;`
365			`end`
366			`2'b01: begin //write - portb`
367			`oflag<=1;`
368			`grbcw<=2;`
369			`bufferout<=data;`
370			`sel<=3;`
371			`end`
372			`2'b10: begin//write - portc`
373			`oflag<=1;`
374			`gracw<=4;`
375			`grbcw<=4;`
376			`bufferout<=data;`
377			`sel<=3;`
378			`end`
379			`endcase`
380			`end`
381			`end`
382			`always @(posedge nwr) begin`
383			`//write completed event`
384			`if(ncs==0) begin`
385			`extrao<=0;`
386			`extrai<=0;`
387			`firststep<=0;`
388			`nextstep<=0;`
389			`iflag<=0;`
390			`oflag<=0;`
391			`gracw<=0;`
392			`grbcw<=0;`
393			`sel<=0;`
394			`end`
395			`end`
396			`always @(negedge nrd) begin`
397			`//read event`
398			`if(ncs==0) begin`
399			`case (addr)`
400			`2'b11: begin//read - control`
401	3	Malasar	`intdata<=mode;`
402			`iflag<=0;`
403			`oflag<=0;`
404			`extrai<=1;`
405	2	Malasar	`end`
406			`2'b00: begin //read - porta`
407	3	Malasar	`iflag<=1;`
408			`gracw<=3;`
409			`sel<=1;`
410	2	Malasar	`end`
411			`2'b01: begin//read - portb`
412	3	Malasar	`iflag<=1;`
413			`grbcw<=3;`
414			`sel<=1;`
415	2	Malasar	`end`
416			`2'b10: begin//read - portc`
417	3	Malasar	`iflag<=1;`
418			`gracw<=5;`
419			`grbcw<=5;`
420			`sel<=3;`
421	2	Malasar	`end`
422			`endcase`
423			`end`
424			`end`
425			`always @(posedge nrd) begin`
426			`//read completed event`
427			`if(ncs==0) begin`
428			`extrao<=0;`
429			`extrai<=0;`
430			`firststep<=0;`
431			`nextstep<=0;`
432			`iflag<=0;`
433			`oflag<=0;`
434			`gracw<=0;`
435			`grbcw<=0;`
436			`sel<=0;`
437			`end`
438			`end`
439			`endmodule`

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