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[/] [image_component_labeling_and_feature_extraction/] [trunk/] [ram1w2r.vhd] - Blame information for rev 2

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1 2 malikpearl
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    10:00:30 11/27/2008 
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-- Design Name: 
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-- Module Name:    ram1w2r - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ram1w2r is
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    Port (
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                          addrefa:in  STD_LOGIC_VECTOR (9 downto 0);
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                          addrefb:in  STD_LOGIC_VECTOR (9 downto 0);
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                          doutrefa:out  STD_LOGIC_VECTOR (9 downto 0);
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                          doutrefb:out  STD_LOGIC_VECTOR (9 downto 0);
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                          addrW : in  STD_LOGIC_VECTOR (9 downto 0);
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           din : in  STD_LOGIC_VECTOR (9 downto 0);
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           we : in  STD_LOGIC;
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           addrRA : in  STD_LOGIC_VECTOR (9 downto 0);
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           doutA : out  STD_LOGIC_VECTOR (9 downto 0);
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           addrRB : in  STD_LOGIC_VECTOR (9 downto 0);
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           doutB : out  STD_LOGIC_VECTOR (9 downto 0);
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           clk : in  STD_LOGIC);
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end ram1w2r;
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architecture Behavioral of ram1w2r is
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type ram_type is array(1023 downto 0) of std_logic_vector(9 downto 0);
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signal ram_array : ram_type:=(others=>(others=>'0'));
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begin
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doutrefa <= ram_array(conv_integer(addrefa));--for reading the memory asynchronously
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doutrefb <= ram_array(conv_integer(addrefb));
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        process(clk)
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        begin
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                if clk'event and clk ='1' then
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                        if we='1' then
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                                ram_array(conv_integer(addrW)) <= din;
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                        end if;
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                        doutA <= ram_array(conv_integer(addrRA));
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                        doutB <= ram_array(conv_integer(addrRB));
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                end if;
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        end process;
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end Behavioral;
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