Subversion Repositories integer_square_root

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer: Yihua Liu

//

// Create Date: 2022/10/14 01:01:28

// Design Name:

// Module Name: testbench

// Project Name: lab_3_b

// Target Devices: xczu7eg-ffvf1517-2-i

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Revision 0.02 - Update Testbench

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module testbench();

        logic [63:0] test_input;

        logic clock, reset, quit;

        logic [31:0] result;

        logic done;

        integer i;

    ISR UUT(

        .reset(reset),

        .value(test_input),

        .clock(clock),

        .result(result),

        .done(done)

    );

        task compare_correct_result;

                input [63:0] value;

                input [31:0] result;

                logic [31:0] guess;

                logic [63:0] multi;

                begin

                        // First, calculate the correct result

                        guess = 32'h8000_0000;

                        for (i = 0; i <= 31; i = i + 1) begin

                                guess[31 - i] = 1'b1;

                                multi = {32'b0, guess};

                                if ((multi * multi) > value) begin

                                        guess[31 - i] = 1'b0;

                                end

                        end

                        // Then, compare the result with the correct one

                        if (result == guess) begin

                        end

                        else begin

                                $display("@@@Failed");

                                $display("Incorrect at time %4.0f",$time);

                                $display("corrent_result = %h result = %h", guess, result);

                                $finish;

                        end

                end

        endtask

        always begin

                #250;

                clock = ~clock;

        end

        // Some users have had problems just using "@(posedge done)" because their

        // "done" signals glitch (even though they are the output of a register). This

        // prevents that by making sure "done" is high at the clock edge.

        task wait_until_done;

                forever begin : wait_loop

                        @(posedge done);

                        @(negedge clock);

                        if (done) disable wait_until_done;

                end

        endtask

        initial begin

                $dumpvars;

                $monitor("Time:%4.0f done:%b input:%h result:%h ",$time, done, test_input, result);

                reset = 0;

                clock = 0;

                // First some special cases

        test_input = 64'h0000_0000_0000_03E9;

                @(negedge clock);

                reset = 1;

                @(negedge clock);

                reset = 0;

                wait_until_done();

                $display("Calculate done!");

                compare_correct_result(test_input, result);

                @(negedge clock);

                reset = 1;

                test_input = 64'hFFFF_FFFF_FFFF_FFFF;

                @(negedge clock);

                reset = 0;

                wait_until_done();

                compare_correct_result(test_input, result);

                @(negedge clock);

                reset = 1;

                test_input = 64'h0000_0000_0000_0000;

                @(negedge clock);

                reset = 0;

                wait_until_done();

                compare_correct_result(test_input, result);

                // Then some random tests

                @(negedge clock);

                reset = 1;

                @(negedge clock);

                quit = 0;

                quit <= #100000 1;

                while (~quit) begin

                        reset = 1;

                        test_input = {$random, $random};

                        @(negedge clock);

                        reset = 0;

                        wait_until_done();

                        compare_correct_result(test_input, result);

                end

        @(negedge clock);

        reset = 1;

        @(negedge clock);

        $display("@@@Passed");

                $finish;

        end

endmodule