Subversion Repositories iota_pow_vhdl

# -------------------------------------------------------------------------- #

#

# Copyright (C) 2017  Intel Corporation. All rights reserved.

# Your use of Intel Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Intel Program License

# Subscription Agreement, the Intel Quartus Prime License Agreement,

# the Intel FPGA IP License Agreement, or other applicable license

# agreement, including, without limitation, that your use is for

# the sole purpose of programming logic devices manufactured by

# Intel and sold by Intel or its authorized distributors.  Please

# refer to the applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus Prime

# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition

# Date created = 10:09:41  April 23, 2018

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               curl-cyclone10_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus Prime software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone 10 LP"

set_global_assignment -name DEVICE 10CL025YE144C8G

set_global_assignment -name TOP_LEVEL_ENTITY de1

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0

set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:09:41  APRIL 23, 2018"

set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name VHDL_FILE spi_slave.vhd

set_global_assignment -name VHDL_FILE de1.vhd

set_global_assignment -name VHDL_FILE index_table.vhd

set_global_assignment -name VHDL_FILE curl.vhd

set_global_assignment -name QIP_FILE pll.qip

set_location_assignment PIN_52 -to CLOCK_50

set_location_assignment PIN_100 -to spi_miso

set_location_assignment PIN_99 -to spi_mosi

set_location_assignment PIN_98 -to spi_sck

set_location_assignment PIN_101 -to spi_ss

set_location_assignment PIN_72 -to reset

set_location_assignment PIN_68 -to led_running

set_location_assignment PIN_66 -to led_overflow

set_location_assignment PIN_67 -to led_found

set_global_assignment -name ENABLE_OCT_DONE OFF

set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"

set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"

set_global_assignment -name USE_CONFIGURATION_DEVICE OFF

set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"

set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_location_assignment PIN_12 -to ~ALTERA_DCLK~

set_location_assignment PIN_13 -to ~ALTERA_DATA0~

set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION AUTO

set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON

set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON

set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON

set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS

set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON

set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS OFF

set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name SMART_RECOMPILE ON

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON

set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON

set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM

set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL

set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON

set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON

set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

set_global_assignment -name MUX_RESTRUCTURE OFF

set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF

set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF

set_global_assignment -name AUTO_RAM_RECOGNITION ON

set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 8.0

set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION AUTOMATICALLY

set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"

set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"

set_global_assignment -name ALLOW_REGISTER_DUPLICATION OFF

set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF

set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 16.0

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top