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https://opencores.org/ocsvn/irda/irda/trunk
[/] [irda/] [web_uploads/] [index.shtml] - Blame information for rev 18
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<!--# set var="title" value="IrDA Controller WISHBONE compatible core" -->
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<!--# include virtual="/ssi/ssi_start.shtml" -->
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<font size=+2 color=#bf0000><b>
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IrDA Controller WISHBONE compatible core.
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</font></b><p>
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<font size=+1><b>
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General
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</b></font><p>
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This core implements IrDA communication in three modes :<BR>
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<B>SIR</B> - Slow IR - using a 16550 UART internally to communicate at speeds up to 115.2Kbps.<BR>
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<B>MIR</B> - Medium speed IR - speed of 0.576Mbps and 1.152Mbps.<BR>
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<B>FIR</B> - Highest speed communication at the rate of 4Mbps.
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<P>
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<font size=+1><b>
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Current Status
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</b></font><p>
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The core is mostly functional, at least in the SIR and MIR modes.
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It being debugged.<BR>
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The documentation of the core is not yet up to date, especially the clock
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dividing mechanism, which is totally different from what is currently
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written in the documentation. I will update it soon.
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<P>
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Developer:Jacob Gorban, <A HREF="mailto:gorban@opencores.org_NOSPAM">gorban@opencores.org_NOSPAM</A>.
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<!--# include virtual="/ssi/ssi_end.shtml" -->
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