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[/] [jt51/] [trunk/] [contra/] [fsm_control.v] - Blame information for rev 3

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`timescale 1ns / 1ps
 
module fsm_control(
        input           clk,
        input           clk_cpu,
        input           rst,
        input           jt_sample,
        // Sound
        output reg      [ 7:0] sound_latch,
        input           [15:0] jt_left,
        input           [15:0] jt_right,
        output reg      irq,
        input           clear_irq,
        // Program
        output reg      cpu_rst,
        output          rom_prog,
        output reg      rom_wr,
        output reg [14:0] rom_addr,
        output reg [7:0]  rom_data,
        // UART wires
        input           uart_rx,
        output          uart_tx
);
 
 
// UART control
wire    [7:0]    uart_rx_data;
reg             [7:0]    uart_tx_data;
wire                    uart_received, uart_error;
reg                             uart_tx_wr;
wire                    uart_tx_done;
reg             [1:0]    send_st;
 
parameter TX_IDLE=0, TX_WAIT_LSB=1, TX_WAIT_MSB=2;
 
reg     [15:0]   left, right, mono;
reg                     sample;
 
always @(*) { left, right, sample } <= { jt_left, jt_right, jt_sample };
always @(*) mono <= (left+right)>>1;
 
// Send music to computer
reg     last_sample;
 
always @(posedge clk or posedge rst) begin
        if( rst ) begin
                uart_tx_wr      <= 1'b0;
                send_st         <= TX_IDLE;
        end
        else begin
                last_sample <= sample;
                case( send_st )
                        TX_IDLE:
                                if( sample && !last_sample ) begin
                                        send_st         <= TX_WAIT_LSB;
                                        uart_tx_data<= mono[7:0];
                                        uart_tx_wr      <= 1'b1;
                                end
                        TX_WAIT_LSB: begin
                                uart_tx_wr      <= 1'b0;
                                if( uart_tx_done ) begin
                                        send_st         <= TX_WAIT_MSB;
                                        uart_tx_data<= mono[15:8];
                                        uart_tx_wr      <= 1'b1;
                                end
                        end
                        TX_WAIT_MSB: begin
                                uart_tx_wr      <= 1'b0;
                                if( uart_tx_done )
                                        send_st         <= TX_IDLE;
                        end
                endcase
        end
end
 
reg     set_irq;
 
always @(posedge clk_cpu or posedge rst ) begin
        if( rst )
                irq <= 1'b0;
        else begin
                if(set_irq) irq<=1'b1;
                else if(clear_irq ) irq<=1'b0;
        end
end
 
reg [1:0] irq_s;
reg rom_wr_s, prog_done_s, adv_s;
reg advance, prog_done;
 
assign rom_prog = !prog_done;
 
always @(posedge clk or posedge rst ) begin
        if( rst ) begin
                // Sound
                sound_latch <= 8'h0;
                set_irq     <= 1'b0;
                cpu_rst         <= 1'b1;
        end
        else begin
                irq_s <= { irq_s[0], irq };
                rom_wr_s <= rom_wr;
                prog_done_s <= prog_done;
                if( uart_received && !uart_error ) begin
                        if( prog_done ) begin
                                        sound_latch <= uart_rx_data;
                                        set_irq     <= 1'b1;
                                end
                        else begin
                                        advance         <= 1'b1;
                                end
        end
                else begin
                        cpu_rst <= !prog_done;
                        if(irq_s[1]) set_irq <= 1'b0;
                        if(rom_wr_s ) advance <= 1'b0;
                end
        end
end
 
reg     prog_st;
 
parameter WAIT=1, NEXT=0;
 
always @(posedge clk_cpu or posedge rst )
        if( rst ) begin
                prog_st <= WAIT;
                rom_wr  <= 1'b0;
                prog_done<= 1'b0;
                `ifdef FASTSIM
                rom_addr<= 15'h7FF0;
                `else
                rom_addr<= 15'h0;
                `endif
        end
        else begin
                adv_s <= advance;
                case( prog_st )
                        NEXT: begin
                                { prog_done,rom_addr } <= rom_addr + 1'b1;
                                rom_wr  <= 1'b0;
                                prog_st <= WAIT;
                                end
                        WAIT: if( adv_s ) begin
                                        rom_wr          <= 1'b1;
                                        rom_data        <= uart_rx_data;
                                        prog_st         <= NEXT;
                                end
                endcase
        end
 
 
uart_transceiver u_uart(
        .sys_rst( rst ),
        .sys_clk( clk ),
 
        .uart_rx(uart_rx),
        .uart_tx(uart_tx),
 
        // 461 kbps @ 50MHz
        // .clk_divider(  5'd6 ), 
        // 921.6 kbps @ 50MHz
        .clk_divider(  5'd3 ),
        .uart_divider( 5'd17 ),
 
        .rx_data( uart_rx_data ),
        .rx_done( uart_received ),
        .rx_error( uart_error ),
 
        .tx_data        ( uart_tx_data  ),
        .tx_wr          ( uart_tx_wr    ),
        .tx_done        ( uart_tx_done  )
);
 
 
endmodule

Line No.	Rev	Author	Line
1	3	gryzor	`timescale 1ns / 1ps
2
3			`module fsm_control(`
4			`input clk,`
5			`input clk_cpu,`
6			`input rst,`
7			`input jt_sample,`
8			`// Sound`
9			`output reg [ 7:0] sound_latch,`
10			`input [15:0] jt_left,`
11			`input [15:0] jt_right,`
12			`output reg irq,`
13			`input clear_irq,`
14			`// Program`
15			`output reg cpu_rst,`
16			`output rom_prog,`
17			`output reg rom_wr,`
18			`output reg [14:0] rom_addr,`
19			`output reg [7:0] rom_data,`
20			`// UART wires`
21			`input uart_rx,`
22			`output uart_tx`
23			`);`
24
25
26			`// UART control`
27			`wire [7:0] uart_rx_data;`
28			`reg [7:0] uart_tx_data;`
29			`wire uart_received, uart_error;`
30			`reg uart_tx_wr;`
31			`wire uart_tx_done;`
32			`reg [1:0] send_st;`
33
34			`parameter TX_IDLE=0, TX_WAIT_LSB=1, TX_WAIT_MSB=2;`
35
36			`reg [15:0] left, right, mono;`
37			`reg sample;`
38
39			`always @(*) { left, right, sample } <= { jt_left, jt_right, jt_sample };`
40			`always @(*) mono <= (left+right)>>1;`
41
42			`// Send music to computer`
43			`reg last_sample;`
44
45			`always @(posedge clk or posedge rst) begin`
46			`if( rst ) begin`
47			`uart_tx_wr <= 1'b0;`
48			`send_st <= TX_IDLE;`
49			`end`
50			`else begin`
51			`last_sample <= sample;`
52			`case( send_st )`
53			`TX_IDLE:`
54			`if( sample && !last_sample ) begin`
55			`send_st <= TX_WAIT_LSB;`
56			`uart_tx_data<= mono[7:0];`
57			`uart_tx_wr <= 1'b1;`
58			`end`
59			`TX_WAIT_LSB: begin`
60			`uart_tx_wr <= 1'b0;`
61			`if( uart_tx_done ) begin`
62			`send_st <= TX_WAIT_MSB;`
63			`uart_tx_data<= mono[15:8];`
64			`uart_tx_wr <= 1'b1;`
65			`end`
66			`end`
67			`TX_WAIT_MSB: begin`
68			`uart_tx_wr <= 1'b0;`
69			`if( uart_tx_done )`
70			`send_st <= TX_IDLE;`
71			`end`
72			`endcase`
73			`end`
74			`end`
75
76			`reg set_irq;`
77
78			`always @(posedge clk_cpu or posedge rst ) begin`
79			`if( rst )`
80			`irq <= 1'b0;`
81			`else begin`
82			`if(set_irq) irq<=1'b1;`
83			`else if(clear_irq ) irq<=1'b0;`
84			`end`
85			`end`
86
87			`reg [1:0] irq_s;`
88			`reg rom_wr_s, prog_done_s, adv_s;`
89			`reg advance, prog_done;`
90
91			`assign rom_prog = !prog_done;`
92
93			`always @(posedge clk or posedge rst ) begin`
94			`if( rst ) begin`
95			`// Sound`
96			`sound_latch <= 8'h0;`
97			`set_irq <= 1'b0;`
98			`cpu_rst <= 1'b1;`
99			`end`
100			`else begin`
101			`irq_s <= { irq_s[0], irq };`
102			`rom_wr_s <= rom_wr;`
103			`prog_done_s <= prog_done;`
104			`if( uart_received && !uart_error ) begin`
105			`if( prog_done ) begin`
106			`sound_latch <= uart_rx_data;`
107			`set_irq <= 1'b1;`
108			`end`
109			`else begin`
110			`advance <= 1'b1;`
111			`end`
112			`end`
113			`else begin`
114			`cpu_rst <= !prog_done;`
115			`if(irq_s[1]) set_irq <= 1'b0;`
116			`if(rom_wr_s ) advance <= 1'b0;`
117			`end`
118			`end`
119			`end`
120
121			`reg prog_st;`
122
123			`parameter WAIT=1, NEXT=0;`
124
125			`always @(posedge clk_cpu or posedge rst )`
126			`if( rst ) begin`
127			`prog_st <= WAIT;`
128			`rom_wr <= 1'b0;`
129			`prog_done<= 1'b0;`
130			`ifdef FASTSIM
131			`rom_addr<= 15'h7FF0;`
132			`else
133			`rom_addr<= 15'h0;`
134			`endif
135			`end`
136			`else begin`
137			`adv_s <= advance;`
138			`case( prog_st )`
139			`NEXT: begin`
140			`{ prog_done,rom_addr } <= rom_addr + 1'b1;`
141			`rom_wr <= 1'b0;`
142			`prog_st <= WAIT;`
143			`end`
144			`WAIT: if( adv_s ) begin`
145			`rom_wr <= 1'b1;`
146			`rom_data <= uart_rx_data;`
147			`prog_st <= NEXT;`
148			`end`
149			`endcase`
150			`end`
151
152
153			`uart_transceiver u_uart(`
154			`.sys_rst( rst ),`
155			`.sys_clk( clk ),`
156
157			`.uart_rx(uart_rx),`
158			`.uart_tx(uart_tx),`
159
160			`// 461 kbps @ 50MHz`
161			`// .clk_divider( 5'd6 ),`
162			`// 921.6 kbps @ 50MHz`
163			`.clk_divider( 5'd3 ),`
164			`.uart_divider( 5'd17 ),`
165
166			`.rx_data( uart_rx_data ),`
167			`.rx_done( uart_received ),`
168			`.rx_error( uart_error ),`
169
170			`.tx_data ( uart_tx_data ),`
171			`.tx_wr ( uart_tx_wr ),`
172			`.tx_done ( uart_tx_done )`
173			`);`
174
175
176			`endmodule`

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[/] [jt51/] [trunk/] [contra/] [fsm_control.v] - Blame information for rev 3