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/*  This file is part of JT51.
 
    JT51 is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
 
    JT51 is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with JT51.  If not, see <http://www.gnu.org/licenses/>.
 
        Author: Jose Tejada Gomez. Twitter: @topapate
        Version: 1.0
        Date: 27-10-2016
        */
 
`timescale 1ns / 1ps
 
/*
 
        tab size 4
 
*/
 
module jt51_envelope(
        `ifdef TEST_SUPPORT
        input                           test_eg,
        `endif
        input                           rst,
        input                           clk,
        input                           zero,
        // envelope configuration
        input           [4:0]    keycode_III,
        input           [4:0]    arate,
        input           [4:0]    rate1,
        input           [4:0]    rate2,
        input           [3:0]    rrate,
        input           [3:0]    d1l,
        input           [1:0]    ks,
        // envelope operation
        input                           keyon,
        input                           keyoff,
        // envelope number
        input           [6:0]    tl,
        input           [6:0]    am,
        input           [1:0]    ams,
        input                           amsen,
        output  reg     [9:0]    eg
);
 
 // eg[9:6] -> direct attenuation (divide by 2)
                // eg[5:0] -> mantisa attenuation (uses LUT)
                // 1 LSB of eg is -0.09257 dB
 
parameter ATTACK=2'd0, DECAY1=2'd1, DECAY2=2'd2, RELEASE=2'd3;
 
reg             [4:0]    d1level;
reg             [2:0]    cnt_V;
reg             [5:0]    rate_IV;
wire    [6:0]    tl_out;
wire    [1:0]    ams_out;
wire                    amsen_out;
reg             [9:0]    eg_in, eg_out_III, eg_out_IV, eg_out_V, eg_out_VI;
wire    [9:0]    eg_out;
reg             [11:0]   sum_eg_tl;
 
reg     step_V, step_VI;
reg             sum_up;
reg             keyon_II, keyon_III, keyon_IV, keyon_V, keyon_VI;
reg             keyoff_II;
reg     [5:0]    rate_V;
reg             [5:1]   rate_VI;
 
reg             [4:0]    rate1_II, rate2_II, arate_II;
reg             [3:0]    rrate_II;
 
// remember: { log_msb, pow_addr } <= log_val[11:0] + { tl, 5'd0 } + { eg, 2'd0 };
 
reg             [1:0]    eg_cnt_base;
reg             [14:0]   eg_cnt;
 
reg             [8:0]    am_final;
 
always @(*) begin : sum_eg_and_tl
        casex( {amsen_out, ams_out } )
                3'b0xx,3'b100: am_final <= 9'd0;
                3'b101: am_final <= { 2'b00, am };
                3'b110: am_final <= { 1'b0, am, 1'b0};
                3'b111: am_final <= { am, 2'b0      };
        endcase
        `ifdef TEST_SUPPORT
        if( test_eg && tl_out!=7'd0 )
                sum_eg_tl <= 11'd0;
        else
        `endif
                sum_eg_tl <= { tl_out,   3'd0 }
                           + eg_in
                                   + { am_final, 1'b0 };
end
 
always @(posedge clk) begin : envelope_counter
        if( rst ) begin
                eg_cnt_base     <= 2'd0;
                eg_cnt          <=15'd0;
        end
        else begin
                if( zero ) begin
                        // envelope counter increases every 3 output samples,
                        // there is one sample every 32 clock ticks
                        if( eg_cnt_base == 2'd2 ) begin
                                eg_cnt          <= eg_cnt + 1'b1;
                                eg_cnt_base     <= 2'd0;
                        end
                        else eg_cnt_base <= eg_cnt_base + 1'b1;
                end
        end
end
 
wire                    cnt_out; // = all_cnt_last[3*31-1:3*30];
 
reg             [6:0]    pre_rate_III;
reg             [4:0]    cfg_III;
wire    [1:0]    ks_III;
 
always @(*) begin : pre_rate_calc
        if( cfg_III == 5'd0 )
                pre_rate_III <= 6'd0;
        else
                case( ks_III )
                        2'd3:   pre_rate_III <= { cfg_III, 1'b0 } + keycode_III;
                        2'd2:   pre_rate_III <= { cfg_III, 1'b0 } + { 1'b0, keycode_III[4:1] };
                        2'd1:   pre_rate_III <= { cfg_III, 1'b0 } + { 2'b0, keycode_III[4:2] };
                        2'd0:   pre_rate_III <= { cfg_III, 1'b0 } + { 3'b0, keycode_III[4:3] };
                endcase
end
 
 
 
reg [7:0]        step_idx;
reg     [1:0]    state_in_III, state_in_IV, state_in_V, state_in_VI;
wire [1:0]       state_out;
 
always @(*) begin : rate_step
        if( rate_V[5:4]==2'b11 ) begin // 0 means 1x, 1 means 2x
                if( rate_V[5:2]==4'hf && state_in_V == ATTACK)
                        step_idx <= 8'b11111111; // Maximum attack speed, rates 60&61
                else
                case( rate_V[1:0] )
                        2'd0: step_idx <= 8'b00000000;
                        2'd1: step_idx <= 8'b10001000; // 2
                        2'd2: step_idx <= 8'b10101010; // 4
                        2'd3: step_idx <= 8'b11101110; // 6
                endcase
        end
        else begin
                if( rate_V[5:2]==4'd0 && state_in_V != ATTACK)
                        step_idx <= 8'b11111110; // limit slowest decay rate_IV
                else
                case( rate_V[1:0] )
                        2'd0: step_idx <= 8'b10101010; // 4
                        2'd1: step_idx <= 8'b11101010; // 5
                        2'd2: step_idx <= 8'b11101110; // 6
                        2'd3: step_idx <= 8'b11111110; // 7
                endcase
        end
        // a rate_IV of zero keeps the level still
        step_V <= rate_V[5:1]==5'd0 ? 1'b0 : step_idx[ cnt_V ];
end
 
 
 
wire    ar_off_VI;
reg             ar_off_III;
 
reg [8:0] ar_sum0;
reg [9:0] ar_result, ar_sum;
 
always @(*) begin : ar_calculation
        casex( rate_VI[5:2] )
                default: ar_sum0 <= eg_out_VI[9:4] + 1'd1;
                4'b1100: ar_sum0 <= eg_out_VI[9:4] + 1'd1;
                4'b1101: ar_sum0 <= eg_out_VI[9:3] + 1'd1;
                4'b111x: ar_sum0 <= eg_out_VI[9:2] + 1'd1;
        endcase
        if( rate_VI[5:4] == 2'b11 )
                ar_sum <= step_VI ? { ar_sum0, 1'b0 } : { 1'b0, ar_sum0 };
        else
                ar_sum <= step_VI ? { 1'b0, ar_sum0 } : 10'd0;
        ar_result <= ar_sum<eg_out_VI ? eg_out_VI-ar_sum : 10'd0;
end
 
always @(posedge clk) begin
        // I
        if( d1l == 4'd15 )
                d1level <= 5'h10; // 48dB 
        else
                d1level <= d1l;
        keyon_II <= keyon;
        keyoff_II<= keyoff;
        { arate_II, rate1_II, rate2_II, rrate_II } <= { arate, rate1, rate2, rrate };
 
        //      II
        ar_off_III      <= arate_II == 5'h1f;
        // trigger release
        if( keyoff_II ) begin
                cfg_III <= { rrate_II, 1'b1 };
                state_in_III <= RELEASE;
        end
        else begin
                // trigger 1st decay
                if( keyon_II ) begin
                        cfg_III <= arate_II;
                        state_in_III <= ATTACK;
                end
                else begin : sel_rate
                        case ( state_out )
                                ATTACK: begin
                                        if( eg_out==10'd0 ) begin
                                                state_in_III <= DECAY1;
                                                cfg_III                  <= rate1_II;
                                        end
                                        else begin
                                                state_in_III <= state_out; // attack
                                                cfg_III                  <= arate_II;
                                        end
                                end
                                DECAY1: begin
                                        if( eg_out[9:5] >= d1level ) begin
                                                cfg_III <= rate2_II;
                                                state_in_III <= DECAY2;
                                        end
                                        else begin
                                                cfg_III <=      rate1_II;
                                                state_in_III <= state_out;      // decay1                               
                                        end
                                end
                                DECAY2: begin
                                                cfg_III <=      rate2_II;
                                                state_in_III <= state_out;      // decay2                               
                                        end
                                RELEASE: begin
                                                cfg_III <=      { rrate_II, 1'b1 };
                                                state_in_III <= state_out;      // release                              
                                        end
                        endcase
                end
        end
 
        keyon_III <= keyon_II;
        eg_out_III <= eg_out;
 
        // III          
        state_in_IV <= state_in_III;
        eg_out_IV <= eg_out_III;
        rate_IV <= pre_rate_III[6] ? 6'd63 : pre_rate_III[5:0];
        keyon_IV <= keyon_III;
 
        // IV
        state_in_V      <= state_in_IV;
        rate_V <= rate_IV;
        keyon_V <= keyon_IV;
        eg_out_V <= eg_out_IV;
    if( state_in_IV == ATTACK )
            casex( rate_IV[5:2] )
                    4'h0: cnt_V <= eg_cnt[13:11];
                    4'h1: cnt_V <= eg_cnt[12:10];
                    4'h2: cnt_V <= eg_cnt[11: 9];
                    4'h3: cnt_V <= eg_cnt[10: 8];
                    4'h4: cnt_V <= eg_cnt[ 9: 7];
                    4'h5: cnt_V <= eg_cnt[ 8: 6];
                    4'h6: cnt_V <= eg_cnt[ 7: 5];
                    4'h7: cnt_V <= eg_cnt[ 6: 4];
                    4'h8: cnt_V <= eg_cnt[ 5: 3];
                    4'h9: cnt_V <= eg_cnt[ 4: 2];
                    4'ha: cnt_V <= eg_cnt[ 3: 1];
                    default: cnt_V <= eg_cnt[ 2: 0];
            endcase
    else
            casex( rate_IV[5:2] )
                    4'h0: cnt_V <= eg_cnt[14:12];
                    4'h1: cnt_V <= eg_cnt[13:11];
                    4'h2: cnt_V <= eg_cnt[12:10];
                    4'h3: cnt_V <= eg_cnt[11: 9];
                    4'h4: cnt_V <= eg_cnt[10: 8];
                    4'h5: cnt_V <= eg_cnt[ 9: 7];
                    4'h6: cnt_V <= eg_cnt[ 8: 6];
                    4'h7: cnt_V <= eg_cnt[ 7: 5];
                    4'h8: cnt_V <= eg_cnt[ 6: 4];
                    4'h9: cnt_V <= eg_cnt[ 5: 3];
                    4'ha: cnt_V <= eg_cnt[ 4: 2];
                    4'hb: cnt_V <= eg_cnt[ 3: 1];
                    default: cnt_V <= eg_cnt[ 2: 0];
            endcase
 
        // V
        state_in_VI <= state_in_V;
        rate_VI <= rate_V[5:1];
        keyon_VI <= keyon_V;
        eg_out_VI <= eg_out_V;
        sum_up <= cnt_V[0] != cnt_out;
        step_VI <= step_V;
        // VI
        if( keyon_VI ) begin
                if( ar_off_VI )
                        eg_in <= 10'd0;
                /*else // todo: verify in silicon
                        eg_in <= 10'h3ff;*/
        end
        else
        if( state_in_VI == ATTACK ) begin
                if( sum_up && eg_out_VI != 10'd0 )
                        if( rate_VI[5:1]==5'd31 )
                                eg_in <= 10'd0;
                        else
                                eg_in <= ar_result;
                else
                        eg_in <= eg_out_VI;
        end
        else begin : DECAY_SUM
                if( sum_up ) begin
                        if ( eg_out_VI<= (10'd1023-10'd8) )
                                case( rate_VI[5:2] )
                                        4'b1100: eg_in <= eg_out_VI + { step_VI, ~step_VI }; // 12
                                        4'b1101: eg_in <= eg_out_VI + { step_VI, ~step_VI, 1'b0 }; // 13
                                        4'b1110: eg_in <= eg_out_VI + { step_VI, ~step_VI, 2'b0 }; // 14
                                        4'b1111: eg_in <= eg_out_VI + 4'd8;// 15
                                        default: eg_in <= eg_out_VI + { step_VI, 1'b0 };
                                endcase
                        else eg_in <= 10'h3FF;
                end
                else eg_in <= eg_out_VI;
        end
        // VII
        eg <= sum_eg_tl[11:10] > 2'b0 ? {10{1'b1}} : sum_eg_tl[9:0];
end
 
// Shift registers
 
jt51_sh #( .width(1), .stages(3) ) u_aroffsh(
        .clk    ( clk           ),
        .din    ( ar_off_III),
        .drop   ( ar_off_VI     )
);
 
jt51_sh #( .width(2), .stages(2) ) u_kssh(
        .clk    ( clk           ),
        .din    ( ks            ),
        .drop   ( ks_III        )
);
 
 
jt51_sh #( .width(10), .stages(6) ) u_tlsh(
        .clk    ( clk           ),
        .din    ( { tl, amsen, ams }    ),
        .drop   ( { tl_out, amsen_out, ams_out }        )
);
 
jt51_sh #( .width(10), .stages(27) ) u_egsh(
        .clk    ( clk           ),
        .din    ( eg_in         ),
        .drop   ( eg_out        )
);
 
jt51_sh #( .width(1), .stages(32) ) u_cntsh(
        .clk    ( clk           ),
        .din    ( cnt_V[0]       ),
        .drop   ( cnt_out       )
);
 
jt51_sh #( .width(2), .stages(31) ) u_statesh(
        .clk    ( clk           ),
        .din    ( state_in_III  ),
        .drop   ( state_out )
);
 
endmodule
 

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[/] [jt51/] [trunk/] [jt51/] [jt51_envelope.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	gryzor	`/* This file is part of JT51.`
2
3			`JT51 is free software: you can redistribute it and/or modify`
4			`it under the terms of the GNU General Public License as published by`
5			`the Free Software Foundation, either version 3 of the License, or`
6			`(at your option) any later version.`
7
8			`JT51 is distributed in the hope that it will be useful,`
9			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
10			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
11			`GNU General Public License for more details.`
12
13			`You should have received a copy of the GNU General Public License`
14			`along with JT51. If not, see <http://www.gnu.org/licenses/>.`
15
16			`Author: Jose Tejada Gomez. Twitter: @topapate`
17			`Version: 1.0`
18			`Date: 27-10-2016`
19			`*/`
20
21			`timescale 1ns / 1ps
22
23			`/*`
24
25			`tab size 4`
26
27			`*/`
28
29			`module jt51_envelope(`
30			`ifdef TEST_SUPPORT
31			`input test_eg,`
32			`endif
33			`input rst,`
34			`input clk,`
35			`input zero,`
36			`// envelope configuration`
37			`input [4:0] keycode_III,`
38			`input [4:0] arate,`
39			`input [4:0] rate1,`
40			`input [4:0] rate2,`
41			`input [3:0] rrate,`
42			`input [3:0] d1l,`
43			`input [1:0] ks,`
44			`// envelope operation`
45			`input keyon,`
46			`input keyoff,`
47			`// envelope number`
48			`input [6:0] tl,`
49			`input [6:0] am,`
50			`input [1:0] ams,`
51			`input amsen,`
52			`output reg [9:0] eg`
53			`);`
54
55			`// eg[9:6] -> direct attenuation (divide by 2)`
56			`// eg[5:0] -> mantisa attenuation (uses LUT)`
57			`// 1 LSB of eg is -0.09257 dB`
58
59			`parameter ATTACK=2'd0, DECAY1=2'd1, DECAY2=2'd2, RELEASE=2'd3;`
60
61			`reg [4:0] d1level;`
62			`reg [2:0] cnt_V;`
63			`reg [5:0] rate_IV;`
64			`wire [6:0] tl_out;`
65			`wire [1:0] ams_out;`
66			`wire amsen_out;`
67			`reg [9:0] eg_in, eg_out_III, eg_out_IV, eg_out_V, eg_out_VI;`
68			`wire [9:0] eg_out;`
69			`reg [11:0] sum_eg_tl;`
70
71			`reg step_V, step_VI;`
72			`reg sum_up;`
73			`reg keyon_II, keyon_III, keyon_IV, keyon_V, keyon_VI;`
74			`reg keyoff_II;`
75			`reg [5:0] rate_V;`
76			`reg [5:1] rate_VI;`
77
78			`reg [4:0] rate1_II, rate2_II, arate_II;`
79			`reg [3:0] rrate_II;`
80
81			`// remember: { log_msb, pow_addr } <= log_val[11:0] + { tl, 5'd0 } + { eg, 2'd0 };`
82
83			`reg [1:0] eg_cnt_base;`
84			`reg [14:0] eg_cnt;`
85
86			`reg [8:0] am_final;`
87
88			`always @(*) begin : sum_eg_and_tl`
89			`casex( {amsen_out, ams_out } )`
90			`3'b0xx,3'b100: am_final <= 9'd0;`
91			`3'b101: am_final <= { 2'b00, am };`
92			`3'b110: am_final <= { 1'b0, am, 1'b0};`
93			`3'b111: am_final <= { am, 2'b0 };`
94			`endcase`
95			`ifdef TEST_SUPPORT
96			`if( test_eg && tl_out!=7'd0 )`
97			`sum_eg_tl <= 11'd0;`
98			`else`
99			`endif
100			`sum_eg_tl <= { tl_out, 3'd0 }`
101			`+ eg_in`
102			`+ { am_final, 1'b0 };`
103			`end`
104
105			`always @(posedge clk) begin : envelope_counter`
106			`if( rst ) begin`
107			`eg_cnt_base <= 2'd0;`
108			`eg_cnt <=15'd0;`
109			`end`
110			`else begin`
111			`if( zero ) begin`
112			`// envelope counter increases every 3 output samples,`
113			`// there is one sample every 32 clock ticks`
114			`if( eg_cnt_base == 2'd2 ) begin`
115			`eg_cnt <= eg_cnt + 1'b1;`
116			`eg_cnt_base <= 2'd0;`
117			`end`
118			`else eg_cnt_base <= eg_cnt_base + 1'b1;`
119			`end`
120			`end`
121			`end`
122
123			`wire cnt_out; // = all_cnt_last[331-1:330];`
124
125			`reg [6:0] pre_rate_III;`
126			`reg [4:0] cfg_III;`
127			`wire [1:0] ks_III;`
128
129			`always @(*) begin : pre_rate_calc`
130			`if( cfg_III == 5'd0 )`
131			`pre_rate_III <= 6'd0;`
132			`else`
133			`case( ks_III )`
134			`2'd3: pre_rate_III <= { cfg_III, 1'b0 } + keycode_III;`
135			`2'd2: pre_rate_III <= { cfg_III, 1'b0 } + { 1'b0, keycode_III[4:1] };`
136			`2'd1: pre_rate_III <= { cfg_III, 1'b0 } + { 2'b0, keycode_III[4:2] };`
137			`2'd0: pre_rate_III <= { cfg_III, 1'b0 } + { 3'b0, keycode_III[4:3] };`
138			`endcase`
139			`end`
140
141
142
143			`reg [7:0] step_idx;`
144			`reg [1:0] state_in_III, state_in_IV, state_in_V, state_in_VI;`
145			`wire [1:0] state_out;`
146
147			`always @(*) begin : rate_step`
148			`if( rate_V[5:4]==2'b11 ) begin // 0 means 1x, 1 means 2x`
149			`if( rate_V[5:2]==4'hf && state_in_V == ATTACK)`
150			`step_idx <= 8'b11111111; // Maximum attack speed, rates 60&61`
151			`else`
152			`case( rate_V[1:0] )`
153			`2'd0: step_idx <= 8'b00000000;`
154			`2'd1: step_idx <= 8'b10001000; // 2`
155			`2'd2: step_idx <= 8'b10101010; // 4`
156			`2'd3: step_idx <= 8'b11101110; // 6`
157			`endcase`
158			`end`
159			`else begin`
160			`if( rate_V[5:2]==4'd0 && state_in_V != ATTACK)`
161			`step_idx <= 8'b11111110; // limit slowest decay rate_IV`
162			`else`
163			`case( rate_V[1:0] )`
164			`2'd0: step_idx <= 8'b10101010; // 4`
165			`2'd1: step_idx <= 8'b11101010; // 5`
166			`2'd2: step_idx <= 8'b11101110; // 6`
167			`2'd3: step_idx <= 8'b11111110; // 7`
168			`endcase`
169			`end`
170			`// a rate_IV of zero keeps the level still`
171			`step_V <= rate_V[5:1]==5'd0 ? 1'b0 : step_idx[ cnt_V ];`
172			`end`
173
174
175
176			`wire ar_off_VI;`
177			`reg ar_off_III;`
178
179			`reg [8:0] ar_sum0;`
180			`reg [9:0] ar_result, ar_sum;`
181
182			`always @(*) begin : ar_calculation`
183			`casex( rate_VI[5:2] )`
184			`default: ar_sum0 <= eg_out_VI[9:4] + 1'd1;`
185			`4'b1100: ar_sum0 <= eg_out_VI[9:4] + 1'd1;`
186			`4'b1101: ar_sum0 <= eg_out_VI[9:3] + 1'd1;`
187			`4'b111x: ar_sum0 <= eg_out_VI[9:2] + 1'd1;`
188			`endcase`
189			`if( rate_VI[5:4] == 2'b11 )`
190			`ar_sum <= step_VI ? { ar_sum0, 1'b0 } : { 1'b0, ar_sum0 };`
191			`else`
192			`ar_sum <= step_VI ? { 1'b0, ar_sum0 } : 10'd0;`
193			`ar_result <= ar_sum<eg_out_VI ? eg_out_VI-ar_sum : 10'd0;`
194			`end`
195
196			`always @(posedge clk) begin`
197			`// I`
198			`if( d1l == 4'd15 )`
199			`d1level <= 5'h10; // 48dB`
200			`else`
201			`d1level <= d1l;`
202			`keyon_II <= keyon;`
203			`keyoff_II<= keyoff;`
204			`{ arate_II, rate1_II, rate2_II, rrate_II } <= { arate, rate1, rate2, rrate };`
205
206			`// II`
207			`ar_off_III <= arate_II == 5'h1f;`
208			`// trigger release`
209			`if( keyoff_II ) begin`
210			`cfg_III <= { rrate_II, 1'b1 };`
211			`state_in_III <= RELEASE;`
212			`end`
213			`else begin`
214			`// trigger 1st decay`
215			`if( keyon_II ) begin`
216			`cfg_III <= arate_II;`
217			`state_in_III <= ATTACK;`
218			`end`
219			`else begin : sel_rate`
220			`case ( state_out )`
221			`ATTACK: begin`
222			`if( eg_out==10'd0 ) begin`
223			`state_in_III <= DECAY1;`
224			`cfg_III <= rate1_II;`
225			`end`
226			`else begin`
227			`state_in_III <= state_out; // attack`
228			`cfg_III <= arate_II;`
229			`end`
230			`end`
231			`DECAY1: begin`
232			`if( eg_out[9:5] >= d1level ) begin`
233			`cfg_III <= rate2_II;`
234			`state_in_III <= DECAY2;`
235			`end`
236			`else begin`
237			`cfg_III <= rate1_II;`
238			`state_in_III <= state_out; // decay1`
239			`end`
240			`end`
241			`DECAY2: begin`
242			`cfg_III <= rate2_II;`
243			`state_in_III <= state_out; // decay2`
244			`end`
245			`RELEASE: begin`
246			`cfg_III <= { rrate_II, 1'b1 };`
247			`state_in_III <= state_out; // release`
248			`end`
249			`endcase`
250			`end`
251			`end`
252
253			`keyon_III <= keyon_II;`
254			`eg_out_III <= eg_out;`
255
256			`// III`
257			`state_in_IV <= state_in_III;`
258			`eg_out_IV <= eg_out_III;`
259			`rate_IV <= pre_rate_III[6] ? 6'd63 : pre_rate_III[5:0];`
260			`keyon_IV <= keyon_III;`
261
262			`// IV`
263			`state_in_V <= state_in_IV;`
264			`rate_V <= rate_IV;`
265			`keyon_V <= keyon_IV;`
266			`eg_out_V <= eg_out_IV;`
267			`if( state_in_IV == ATTACK )`
268			`casex( rate_IV[5:2] )`
269			`4'h0: cnt_V <= eg_cnt[13:11];`
270			`4'h1: cnt_V <= eg_cnt[12:10];`
271			`4'h2: cnt_V <= eg_cnt[11: 9];`
272			`4'h3: cnt_V <= eg_cnt[10: 8];`
273			`4'h4: cnt_V <= eg_cnt[ 9: 7];`
274			`4'h5: cnt_V <= eg_cnt[ 8: 6];`
275			`4'h6: cnt_V <= eg_cnt[ 7: 5];`
276			`4'h7: cnt_V <= eg_cnt[ 6: 4];`
277			`4'h8: cnt_V <= eg_cnt[ 5: 3];`
278			`4'h9: cnt_V <= eg_cnt[ 4: 2];`
279			`4'ha: cnt_V <= eg_cnt[ 3: 1];`
280			`default: cnt_V <= eg_cnt[ 2: 0];`
281			`endcase`
282			`else`
283			`casex( rate_IV[5:2] )`
284			`4'h0: cnt_V <= eg_cnt[14:12];`
285			`4'h1: cnt_V <= eg_cnt[13:11];`
286			`4'h2: cnt_V <= eg_cnt[12:10];`
287			`4'h3: cnt_V <= eg_cnt[11: 9];`
288			`4'h4: cnt_V <= eg_cnt[10: 8];`
289			`4'h5: cnt_V <= eg_cnt[ 9: 7];`
290			`4'h6: cnt_V <= eg_cnt[ 8: 6];`
291			`4'h7: cnt_V <= eg_cnt[ 7: 5];`
292			`4'h8: cnt_V <= eg_cnt[ 6: 4];`
293			`4'h9: cnt_V <= eg_cnt[ 5: 3];`
294			`4'ha: cnt_V <= eg_cnt[ 4: 2];`
295			`4'hb: cnt_V <= eg_cnt[ 3: 1];`
296			`default: cnt_V <= eg_cnt[ 2: 0];`
297			`endcase`
298
299			`// V`
300			`state_in_VI <= state_in_V;`
301			`rate_VI <= rate_V[5:1];`
302			`keyon_VI <= keyon_V;`
303			`eg_out_VI <= eg_out_V;`
304			`sum_up <= cnt_V[0] != cnt_out;`
305			`step_VI <= step_V;`
306			`// VI`
307			`if( keyon_VI ) begin`
308			`if( ar_off_VI )`
309			`eg_in <= 10'd0;`
310			`/*else // todo: verify in silicon`
311			`eg_in <= 10'h3ff;*/`
312			`end`
313			`else`
314			`if( state_in_VI == ATTACK ) begin`
315			`if( sum_up && eg_out_VI != 10'd0 )`
316			`if( rate_VI[5:1]==5'd31 )`
317			`eg_in <= 10'd0;`
318			`else`
319			`eg_in <= ar_result;`
320			`else`
321			`eg_in <= eg_out_VI;`
322			`end`
323			`else begin : DECAY_SUM`
324			`if( sum_up ) begin`
325			`if ( eg_out_VI<= (10'd1023-10'd8) )`
326			`case( rate_VI[5:2] )`
327			`4'b1100: eg_in <= eg_out_VI + { step_VI, ~step_VI }; // 12`
328			`4'b1101: eg_in <= eg_out_VI + { step_VI, ~step_VI, 1'b0 }; // 13`
329			`4'b1110: eg_in <= eg_out_VI + { step_VI, ~step_VI, 2'b0 }; // 14`
330			`4'b1111: eg_in <= eg_out_VI + 4'd8;// 15`
331			`default: eg_in <= eg_out_VI + { step_VI, 1'b0 };`
332			`endcase`
333			`else eg_in <= 10'h3FF;`
334			`end`
335			`else eg_in <= eg_out_VI;`
336			`end`
337			`// VII`
338			`eg <= sum_eg_tl[11:10] > 2'b0 ? {10{1'b1}} : sum_eg_tl[9:0];`
339			`end`
340
341			`// Shift registers`
342
343			`jt51_sh #( .width(1), .stages(3) ) u_aroffsh(`
344			`.clk ( clk ),`
345			`.din ( ar_off_III),`
346			`.drop ( ar_off_VI )`
347			`);`
348
349			`jt51_sh #( .width(2), .stages(2) ) u_kssh(`
350			`.clk ( clk ),`
351			`.din ( ks ),`
352			`.drop ( ks_III )`
353			`);`
354
355
356			`jt51_sh #( .width(10), .stages(6) ) u_tlsh(`
357			`.clk ( clk ),`
358			`.din ( { tl, amsen, ams } ),`
359			`.drop ( { tl_out, amsen_out, ams_out } )`
360			`);`
361
362			`jt51_sh #( .width(10), .stages(27) ) u_egsh(`
363			`.clk ( clk ),`
364			`.din ( eg_in ),`
365			`.drop ( eg_out )`
366			`);`
367
368			`jt51_sh #( .width(1), .stages(32) ) u_cntsh(`
369			`.clk ( clk ),`
370			`.din ( cnt_V[0] ),`
371			`.drop ( cnt_out )`
372			`);`
373
374			`jt51_sh #( .width(2), .stages(31) ) u_statesh(`
375			`.clk ( clk ),`
376			`.din ( state_in_III ),`
377			`.drop ( state_out )`
378			`);`
379
380			`endmodule`
381