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/*  This file is part of JT51.
 
    JT51 is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
 
    JT51 is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with JT51.  If not, see <http://www.gnu.org/licenses/>.
 
        Author: Jose Tejada Gomez. Twitter: @topapate
        Version: 1.0
        Date: 27-10-2016
        */
 
`timescale 1ns / 1ps
 
module jt51_reg(
        input                   rst,
        input                   clk,            // P1
        input   [7:0]    d_in,
 
        input                   up_rl,
        input                   up_kc,
        input                   up_kf,
        input                   up_pms,
        input                   up_dt1,
        input                   up_tl,
        input                   up_ks,
        input                   up_amsen,
        input                   up_dt2,
        input                   up_d1l,
        input                   up_kon,
        input   [1:0]    op,             // operator to update
        input   [2:0]    ch,             // channel to update
 
        input                   csm,
        input                   flag_A,
 
        output                  busy,
        output  [1:0]    rl_out,
        output  [2:0]    fb_out,
        output  [2:0]    con_out,
        output  [6:0]    kc_out,
        output  [5:0]    kf_out,
        output  [2:0]    pms_out,
        output  [1:0]    ams_out,
        output  [2:0]    dt1_out,
        output  [3:0]    mul_out,
        output  [6:0]    tl_out,
        output  [1:0]    ks_out,
        output  [4:0]    ar_out,
        output                  amsen_out,
        output  [4:0]    d1r_out,
        output  [1:0]    dt2_out,
        output  [4:0]    d2r_out,
        output  [3:0]    d1l_out,
        output  [3:0]    rr_out,
        output                  kon_out,
        output                  koff_out,
 
        output  [1:0]    cur_op,
 
        output  reg             zero
);
 
reg             kon, koff;
reg [1:0] csm_state;
reg     [4:0] csm_cnt;
 
wire csm_kon  = csm_state[0];
wire csm_koff = csm_state[1];
 
assign kon_out  = kon  | csm_kon;
assign koff_out = koff | csm_koff;
 
wire    [1:0]    rl_in   = d_in[7:6];
wire    [2:0]    fb_in   = d_in[5:3];
wire    [2:0]    con_in  = d_in[2:0];
wire    [6:0]    kc_in   = d_in[6:0];
wire    [5:0]    kf_in   = d_in[7:2];
wire    [2:0]    pms_in  = d_in[6:4];
wire    [1:0]    ams_in  = d_in[1:0];
wire    [2:0]    dt1_in  = d_in[6:4];
wire    [3:0]    mul_in  = d_in[3:0];
wire    [6:0]    tl_in   = d_in[6:0];
wire    [1:0]    ks_in   = d_in[7:6];
wire    [4:0]    ar_in   = d_in[4:0];
wire                    amsen_in= d_in[7];
wire    [4:0]    d1r_in  = d_in[4:0];
wire    [1:0]    dt2_in  = d_in[7:6];
wire    [4:0]    d2r_in  = d_in[4:0];
wire    [3:0]    d1l_in  = d_in[7:4];
wire    [3:0]    rr_in   = d_in[3:0];
 
wire up =       up_rl | up_kc | up_kf | up_pms | up_dt1 | up_tl |
                        up_ks | up_amsen | up_dt2 | up_d1l;
 
reg     [4:0]    cnt, next, cur;
reg                     last, last_kon;
reg     [1:0]    cnt_kon;
reg                     busy_op, busy_kon;
 
assign busy = busy_op | busy_kon;
 
assign cur_op = cur[4:3];
 
always @(*) begin
        next <= cur +1'b1;
end
 
wire    [4:0] abs        = { op, ch };
wire    update_op       = abs == cur;
wire    update_ch       = ch  == cur[2:0];
 
wire up_rl_ch   = up_rl         & update_ch;
wire up_kc_ch   = up_kc         & update_ch;
wire up_kf_ch   = up_kf         & update_ch;
wire up_pms_ch  = up_pms        & update_ch;
wire up_dt1_op  = up_dt1        & update_op;
wire up_tl_op   = up_tl         & update_op;
wire up_ks_op   = up_ks         & update_op;
wire up_amsen_op= up_amsen      & update_op;
wire up_dt2_op  = up_dt2        & update_op;
wire up_d1l_op  = up_d1l        & update_op;
 
 
 
always @(posedge clk) begin : up_counter
        if( rst ) begin
                cnt             <= 5'h0;
                cur             <= 5'h0;
                last    <= 1'b0;
                zero    <= 1'b0;
        busy_op <= 1'b0;
        end
        else begin
                cur             <= next;
                zero    <= cur== 5'd0;
                last    <= up;
                if( up && !last ) begin
                        cnt             <= cur;
                        busy_op <= 1'b1;
                end
                else if( cnt == cur ) busy_op <= 1'b0;
        end
end
 
 
always @(posedge clk) begin : keyon_csm
        if( rst ) begin
                csm_state       <= 2'b0;
                csm_cnt         <= 5'd0;
        end
        else begin
                if( csm && flag_A ) begin
                        csm_state <= 2'b1;
                        csm_cnt   <= 5'd0;
                end
                else begin
                        if( csm_cnt==5'd31 ) begin
                                if( csm_state==2'b1 ) begin
                                        csm_state <= 2'b10;
                                        csm_cnt <= 5'd0;
                                end
                                else csm_state <= 2'b0;
                        end
                        else csm_cnt <= csm_cnt+1'b1;
                end
        end
end
 
reg     [3:0] kon_op;
 
always @(posedge clk) begin : keyon
        if( rst ) begin
                last_kon <= 1'b0;
        busy_kon <= 1'b0;
        kon_op   <= 4'd0;
        { kon, koff } <= 2'd0;
        end
        else begin
                last_kon<= up_kon;
                if( up_kon && !last_kon ) begin
                        busy_kon  <= 1'b1;
                        kon_op[0] <= d_in[5]; // M2
                        kon_op[1] <= d_in[4]; // C1
                        kon_op[2] <= d_in[6]; // C2
                        kon_op[3] <= d_in[3]; // M1
                        cnt_kon   <= 2'd0;
            { kon, koff } <= 2'd0;
                end
                else
                if( busy_kon && next[2:0]==d_in[2:0]) begin
                        case( cnt_kon )
                                2'd0: // M2
                                        if(next[4:3]==2'd1) begin
                                                { kon, koff } <= { kon_op[0], ~kon_op[0] };
                                                cnt_kon <= 2'd1;
                                        end
                2'd1: // C1
                                        if(next[4:3]==2'd2) begin
                                                { kon, koff } <= { kon_op[1], ~kon_op[1] };
                                                cnt_kon <= 2'd2;
                                        end
                2'd2: // C2
                                        if(next[4:3]==2'd3) begin
                                                { kon, koff } <= { kon_op[2], ~kon_op[2] };
                                                cnt_kon <= 2'd3;
                                        end
                2'd3: // M1
                                        if(next[4:3]==2'd0) begin
                                                { kon, koff } <= { kon_op[3], ~kon_op[3] };
                                                busy_kon <= 1'b0;
                                        end
                        endcase
                end
        else { kon, koff } <= 2'd0;
        end
end
 
// memory for OP registers
 
reg  [41:0] reg_op[31:0];
reg  [41:0] reg_out;
 
assign { dt1_out, mul_out, tl_out, ks_out, ar_out, amsen_out, d1r_out,
        dt2_out, d2r_out, d1l_out, rr_out } = reg_out;
 
wire [41:0] reg_in = {
                                        up_dt1_op       ? { dt1_in, mul_in}             : { dt1_out, mul_out },
                                        up_tl_op        ? tl_in                                 : tl_out,
                    up_ks_op    ? { ks_in, ar_in }              : { ks_out, ar_out },
                    up_amsen_op ? { amsen_in, d1r_in }  : { amsen_out, d1r_out },
                    up_dt2_op   ? { dt2_in, d2r_in }    : { dt2_out, d2r_out },
                    up_d1l_op   ? { d1l_in, rr_in }             : { d1l_out, rr_out } };
 
wire opdata_wr = |{ up_dt1_op, up_tl_op, up_ks_op, up_amsen_op, up_dt2_op, up_d1l_op };
 
always @(posedge clk) begin
        reg_out         <= reg_op[next];
    if( opdata_wr )
        reg_op[cur]     <= reg_in;
end
 
// memory for CH registers
 
reg [25:0] reg_ch[7:0];
reg [25:0] reg_ch_out;
wire [25:0] reg_ch_in = {
                up_rl_ch        ? { rl_in, fb_in, con_in }      : { rl_out, fb_out, con_out },
        up_kc_ch        ? kc_in                                         : kc_out,
        up_kf_ch        ? kf_in                                         : kf_out,
        up_pms_ch       ? { pms_in, ams_in }            : { pms_out, ams_out } };
 
assign { rl_out, fb_out, con_out, kc_out, kf_out, pms_out, ams_out } = reg_ch_out;
 
wire [2:0] next_ch = next[2:0];
wire [2:0]  cur_ch =  cur[2:0];
wire chdata_wr = |{up_rl_ch, up_kc_ch, up_kf_ch, up_pms_ch };
 
always @(posedge clk) begin
        reg_ch_out              <= reg_ch[next_ch];
    if( chdata_wr )
        reg_ch[cur_ch]  <= reg_ch_in;
end
 
endmodule

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[/] [jt51/] [trunk/] [jt51/] [jt51_reg.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	gryzor	`/* This file is part of JT51.`
2
3			`JT51 is free software: you can redistribute it and/or modify`
4			`it under the terms of the GNU General Public License as published by`
5			`the Free Software Foundation, either version 3 of the License, or`
6			`(at your option) any later version.`
7
8			`JT51 is distributed in the hope that it will be useful,`
9			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
10			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
11			`GNU General Public License for more details.`
12
13			`You should have received a copy of the GNU General Public License`
14			`along with JT51. If not, see <http://www.gnu.org/licenses/>.`
15
16			`Author: Jose Tejada Gomez. Twitter: @topapate`
17			`Version: 1.0`
18			`Date: 27-10-2016`
19			`*/`
20
21			`timescale 1ns / 1ps
22
23			`module jt51_reg(`
24			`input rst,`
25			`input clk, // P1`
26			`input [7:0] d_in,`
27
28			`input up_rl,`
29			`input up_kc,`
30			`input up_kf,`
31			`input up_pms,`
32			`input up_dt1,`
33			`input up_tl,`
34			`input up_ks,`
35			`input up_amsen,`
36			`input up_dt2,`
37			`input up_d1l,`
38			`input up_kon,`
39			`input [1:0] op, // operator to update`
40			`input [2:0] ch, // channel to update`
41
42			`input csm,`
43			`input flag_A,`
44
45			`output busy,`
46			`output [1:0] rl_out,`
47			`output [2:0] fb_out,`
48			`output [2:0] con_out,`
49			`output [6:0] kc_out,`
50			`output [5:0] kf_out,`
51			`output [2:0] pms_out,`
52			`output [1:0] ams_out,`
53			`output [2:0] dt1_out,`
54			`output [3:0] mul_out,`
55			`output [6:0] tl_out,`
56			`output [1:0] ks_out,`
57			`output [4:0] ar_out,`
58			`output amsen_out,`
59			`output [4:0] d1r_out,`
60			`output [1:0] dt2_out,`
61			`output [4:0] d2r_out,`
62			`output [3:0] d1l_out,`
63			`output [3:0] rr_out,`
64			`output kon_out,`
65			`output koff_out,`
66
67			`output [1:0] cur_op,`
68
69			`output reg zero`
70			`);`
71
72			`reg kon, koff;`
73			`reg [1:0] csm_state;`
74			`reg [4:0] csm_cnt;`
75
76			`wire csm_kon = csm_state[0];`
77			`wire csm_koff = csm_state[1];`
78
79			`assign kon_out = kon \| csm_kon;`
80			`assign koff_out = koff \| csm_koff;`
81
82			`wire [1:0] rl_in = d_in[7:6];`
83			`wire [2:0] fb_in = d_in[5:3];`
84			`wire [2:0] con_in = d_in[2:0];`
85			`wire [6:0] kc_in = d_in[6:0];`
86			`wire [5:0] kf_in = d_in[7:2];`
87			`wire [2:0] pms_in = d_in[6:4];`
88			`wire [1:0] ams_in = d_in[1:0];`
89			`wire [2:0] dt1_in = d_in[6:4];`
90			`wire [3:0] mul_in = d_in[3:0];`
91			`wire [6:0] tl_in = d_in[6:0];`
92			`wire [1:0] ks_in = d_in[7:6];`
93			`wire [4:0] ar_in = d_in[4:0];`
94			`wire amsen_in= d_in[7];`
95			`wire [4:0] d1r_in = d_in[4:0];`
96			`wire [1:0] dt2_in = d_in[7:6];`
97			`wire [4:0] d2r_in = d_in[4:0];`
98			`wire [3:0] d1l_in = d_in[7:4];`
99			`wire [3:0] rr_in = d_in[3:0];`
100
101			`wire up = up_rl \| up_kc \| up_kf \| up_pms \| up_dt1 \| up_tl \|`
102			`up_ks \| up_amsen \| up_dt2 \| up_d1l;`
103
104			`reg [4:0] cnt, next, cur;`
105			`reg last, last_kon;`
106			`reg [1:0] cnt_kon;`
107			`reg busy_op, busy_kon;`
108
109			`assign busy = busy_op \| busy_kon;`
110
111			`assign cur_op = cur[4:3];`
112
113			`always @(*) begin`
114			`next <= cur +1'b1;`
115			`end`
116
117			`wire [4:0] abs = { op, ch };`
118			`wire update_op = abs == cur;`
119			`wire update_ch = ch == cur[2:0];`
120
121			`wire up_rl_ch = up_rl & update_ch;`
122			`wire up_kc_ch = up_kc & update_ch;`
123			`wire up_kf_ch = up_kf & update_ch;`
124			`wire up_pms_ch = up_pms & update_ch;`
125			`wire up_dt1_op = up_dt1 & update_op;`
126			`wire up_tl_op = up_tl & update_op;`
127			`wire up_ks_op = up_ks & update_op;`
128			`wire up_amsen_op= up_amsen & update_op;`
129			`wire up_dt2_op = up_dt2 & update_op;`
130			`wire up_d1l_op = up_d1l & update_op;`
131
132
133
134			`always @(posedge clk) begin : up_counter`
135			`if( rst ) begin`
136			`cnt <= 5'h0;`
137			`cur <= 5'h0;`
138			`last <= 1'b0;`
139			`zero <= 1'b0;`
140			`busy_op <= 1'b0;`
141			`end`
142			`else begin`
143			`cur <= next;`
144			`zero <= cur== 5'd0;`
145			`last <= up;`
146			`if( up && !last ) begin`
147			`cnt <= cur;`
148			`busy_op <= 1'b1;`
149			`end`
150			`else if( cnt == cur ) busy_op <= 1'b0;`
151			`end`
152			`end`
153
154
155			`always @(posedge clk) begin : keyon_csm`
156			`if( rst ) begin`
157			`csm_state <= 2'b0;`
158			`csm_cnt <= 5'd0;`
159			`end`
160			`else begin`
161			`if( csm && flag_A ) begin`
162			`csm_state <= 2'b1;`
163			`csm_cnt <= 5'd0;`
164			`end`
165			`else begin`
166			`if( csm_cnt==5'd31 ) begin`
167			`if( csm_state==2'b1 ) begin`
168			`csm_state <= 2'b10;`
169			`csm_cnt <= 5'd0;`
170			`end`
171			`else csm_state <= 2'b0;`
172			`end`
173			`else csm_cnt <= csm_cnt+1'b1;`
174			`end`
175			`end`
176			`end`
177
178			`reg [3:0] kon_op;`
179
180			`always @(posedge clk) begin : keyon`
181			`if( rst ) begin`
182			`last_kon <= 1'b0;`
183			`busy_kon <= 1'b0;`
184			`kon_op <= 4'd0;`
185			`{ kon, koff } <= 2'd0;`
186			`end`
187			`else begin`
188			`last_kon<= up_kon;`
189			`if( up_kon && !last_kon ) begin`
190			`busy_kon <= 1'b1;`
191			`kon_op[0] <= d_in[5]; // M2`
192			`kon_op[1] <= d_in[4]; // C1`
193			`kon_op[2] <= d_in[6]; // C2`
194			`kon_op[3] <= d_in[3]; // M1`
195			`cnt_kon <= 2'd0;`
196			`{ kon, koff } <= 2'd0;`
197			`end`
198			`else`
199			`if( busy_kon && next[2:0]==d_in[2:0]) begin`
200			`case( cnt_kon )`
201			`2'd0: // M2`
202			`if(next[4:3]==2'd1) begin`
203			`{ kon, koff } <= { kon_op[0], ~kon_op[0] };`
204			`cnt_kon <= 2'd1;`
205			`end`
206			`2'd1: // C1`
207			`if(next[4:3]==2'd2) begin`
208			`{ kon, koff } <= { kon_op[1], ~kon_op[1] };`
209			`cnt_kon <= 2'd2;`
210			`end`
211			`2'd2: // C2`
212			`if(next[4:3]==2'd3) begin`
213			`{ kon, koff } <= { kon_op[2], ~kon_op[2] };`
214			`cnt_kon <= 2'd3;`
215			`end`
216			`2'd3: // M1`
217			`if(next[4:3]==2'd0) begin`
218			`{ kon, koff } <= { kon_op[3], ~kon_op[3] };`
219			`busy_kon <= 1'b0;`
220			`end`
221			`endcase`
222			`end`
223			`else { kon, koff } <= 2'd0;`
224			`end`
225			`end`
226
227			`// memory for OP registers`
228
229			`reg [41:0] reg_op[31:0];`
230			`reg [41:0] reg_out;`
231
232			`assign { dt1_out, mul_out, tl_out, ks_out, ar_out, amsen_out, d1r_out,`
233			`dt2_out, d2r_out, d1l_out, rr_out } = reg_out;`
234
235			`wire [41:0] reg_in = {`
236			`up_dt1_op ? { dt1_in, mul_in} : { dt1_out, mul_out },`
237			`up_tl_op ? tl_in : tl_out,`
238			`up_ks_op ? { ks_in, ar_in } : { ks_out, ar_out },`
239			`up_amsen_op ? { amsen_in, d1r_in } : { amsen_out, d1r_out },`
240			`up_dt2_op ? { dt2_in, d2r_in } : { dt2_out, d2r_out },`
241			`up_d1l_op ? { d1l_in, rr_in } : { d1l_out, rr_out } };`
242
243			`wire opdata_wr = \|{ up_dt1_op, up_tl_op, up_ks_op, up_amsen_op, up_dt2_op, up_d1l_op };`
244
245			`always @(posedge clk) begin`
246			`reg_out <= reg_op[next];`
247			`if( opdata_wr )`
248			`reg_op[cur] <= reg_in;`
249			`end`
250
251			`// memory for CH registers`
252
253			`reg [25:0] reg_ch[7:0];`
254			`reg [25:0] reg_ch_out;`
255			`wire [25:0] reg_ch_in = {`
256			`up_rl_ch ? { rl_in, fb_in, con_in } : { rl_out, fb_out, con_out },`
257			`up_kc_ch ? kc_in : kc_out,`
258			`up_kf_ch ? kf_in : kf_out,`
259			`up_pms_ch ? { pms_in, ams_in } : { pms_out, ams_out } };`
260
261			`assign { rl_out, fb_out, con_out, kc_out, kf_out, pms_out, ams_out } = reg_ch_out;`
262
263			`wire [2:0] next_ch = next[2:0];`
264			`wire [2:0] cur_ch = cur[2:0];`
265			`wire chdata_wr = \|{up_rl_ch, up_kc_ch, up_kf_ch, up_pms_ch };`
266
267			`always @(posedge clk) begin`
268			`reg_ch_out <= reg_ch[next_ch];`
269			`if( chdata_wr )`
270			`reg_ch[cur_ch] <= reg_ch_in;`
271			`end`
272
273			`endmodule`