<b><font size=+2 face="Helvetica, Arial" color=#bf0000>Project Name: IEEE 1149.1 Test Access Port (TAP)</font></b>
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<p>
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<font size=+1><b>Description</b></font>
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<p>This implementation of the Test Access Port (TAP) is fully IEEE 1149.1 compliant. It includes a TAP controller, a 4-bit instruction
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register and three test data registers: idcode register, bypass register and boundary scan register. Boundary scan register is connected to eight
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pins (2 inputs, 2 outputs, 2 tristatable outputs and 2 bidirectional pins). Besides the Verilog code, a BSDL file is also provided. The number of
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pins can be easily increased by following the instructions. The design had been tested with the JTAG Technologies testing equipment (The TAP controller was implemented in
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Xilinx 95144XL). The design will be expanded in the future to support additional instruction and debug capabilities.
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<p>
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Current Status:
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<ul>
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<li><a href="Boundary-Scan%20Architecture.pdf">A description of a Boundary Scan Implementation(57KB)</a> is avaliable in Adobe PDF format.</li>
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<li>Verilog and BSDL files can be accessed via <a href="http://www.opencores.org/cvsweb.shtml/">cvsweb.</a></li>
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<li>Some additional information can be found <a href="http://www.opencores.org/cores/DebugInterface/">here.</a></li>
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</ul>
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<p>
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Next Step:
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<ul>
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<li>Implementing additional instructions.</li>
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<li><a href="http://www.opencores.org/cores/DebugInterface/">JTAG debug interface for the OR1k processor.</a></li>
