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//---------------------------------------------------------------------------
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// keypad_scanner.v -- Small keypad scanner module
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//
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//
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// Description: See description below (which suffices for IP core
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// specification document.)
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//
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// Copyright (C) 2002 John Clayton and OPENCORES.ORG (this Verilog version)
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source.
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// If not, download it from http://www.opencores.org/lgpl.shtml
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//
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//-----------------------------------------------------------------------------
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//
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// Author: John Clayton
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// Date : Jan. 30, 2003
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// Update: Mar. 24, 2003 Copied this file from "serial_divide_uu.v"
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// Stripped out extraneous stuff.
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// Update: Mar. 31, 2003 Finished coding, added function "one_low_among_z"
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// and tested in hardware.
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//
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//-----------------------------------------------------------------------------
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// Description:
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//
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// This module is for reading keypresses on a small matrix-style keypad,
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// keyboard or game controller.
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//
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// In the interest of keeping things simple and generic, this module does not
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// attempt to look at multiple keypresses, whether the key is being depressed
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// or else released, N-key rollover or any other such complicated ideas.
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//
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// In fact, with an X-Y matrix of keys if multiple keys are pressed in
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// different rows of the matrix, which share the same column(s), a situation
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// arises in which it is impossible to detect which keys are pressed...
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// These ambiguous cases do not occur with only 2 keys pressed, but can
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// always happen with 3 keys pressed simultaneously. Please be aware of this!
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//
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// For cases which are not ambiguous, this unit provides a "1" for keys that
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// are pressed, and "0" for keys not pressed. In the ambiguous cases, extra
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// "1" bits appear in the output, even though the corresponding key may not
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// have been pressed.
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//
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// So if all the keys are pressed in one whole row and one whole column,
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// then the output will consist of all "1" bits.
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//
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// The module is termed a "keypad_scanner" because the output, while useful
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// in real-time, is a sampling of the keypad matrix. Each scan produces a
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// single "snapshot" of data containing a unique bit for each key. Each
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// scan is initiated by providing a pulse on the scan_i input. When the
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// scan is complete, the new sampled data is produced on the dat_o bus,
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// and the stb_o output pulses for one clock. The scan_i input is ignored
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// during a scan. If the stb_o output is tied to the scan_i input, then the
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// unit will scan continuously, as fast as it can proceed. Each full scan
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// requires one clock per row scanned.
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//
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// Although the keys are scanned row-by-row, the row data are stored and the
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// results are presented in parallel at a given instant in time. The speed
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// of scanning is programmable by parameters.
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//
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// If the scan speed is reduced to a low enough rate (say 50 full scans per
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// second) then this can also provide a "free" debouncing function.
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// Well, honestly it is not a completely fool-proof switch debounce, since
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// the scan may happen to pick up a bounce as a reading, but most bounce is
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// less than 20ms in duration, so that the chances of anyone caring about this
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// are very slim indeed.
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//
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// In fact, one could launch from here into a full scale discussion of the
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// nature of debouncing, flip-flop metastability issues and the like.
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// But I will forego such a philosophical discussion in order to concentrate
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// on more practical issues.
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//
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// IN ORDER FOR THIS MODULE TO WORK PROPERLY, the column inputs must have
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// pullup resistors on them. The rows simply provide a "low" output which can
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// overcome the pullups and provide for a valid reading at the column inputs.
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// Obviously, the value of the pullups is not critical as long as the row
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// scanning rate is slow enough that the pullups can charge the parasitic
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// capacitance of the keypad column wires in between row scans.
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// Many programmable logic families provide built in pullup resistors which
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// can be selected in the pin-constraints file. These will be more than
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// adequate for the use of this module. Just don't forget to add them, or
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// you will most likely get all "0" output.
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//
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// There are parameters provided in order to set the size of the X-Y key
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// matrix. However, the author was envisioning a small sized keyboard for use
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// with this module. Perhaps the number of keys in the matrix would range
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// from 8 (min.) to about 64 or so. (max.)
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//
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// A matrix larger than this might still work, but there would be a very large
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// bus of outputs coming from the module... so just be aware of it.
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//
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// Parameters are:
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//
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// ROWS_PP -- The number of rows in the keypad matrix
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// COLS_PP -- The number of columns in the keypad matrix
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// ROW_BITS_PP -- The number of bits needed to hold ROWS_PP-1
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// TMR_CLKS_PP -- The number of clk_i edges before the next
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// row is scanned.
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// TMR_BITS_PP -- The number of bits needed to hold TMR_CLKS_PP-1
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//
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//-----------------------------------------------------------------------------
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module keypad_scanner (
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clk_i,
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clk_en_i,
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rst_i,
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scan_i,
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col_i,
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row_o,
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dat_o,
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done_o
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);
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parameter ROWS_PP = 4; // Number of rows to scan
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parameter COLS_PP = 4; // Number of columns to read
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parameter ROW_BITS_PP = 2; // Number of bits needed to hold ROWS_PP-1
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parameter TMR_CLKS_PP = 60000; // Set for 200 scans/sec, 4 rows, 48MHz clk_i
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parameter TMR_BITS_PP = 16; // Number of bits needed to hold TMR_CLKS_PP-1
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// I/O declarations
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input clk_i; // The clock
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input clk_en_i; // Used to qualify clk_i input
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input rst_i; // synchronous reset
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input scan_i; // Used to start a keypad scan
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input [COLS_PP-1:0] col_i; // The column inputs
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output [ROWS_PP-1:0] row_o; // The row outputs
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output [COLS_PP*ROWS_PP-1:0] dat_o; // The output bus
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output done_o; // indicates completion of scan
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reg [COLS_PP*ROWS_PP-1:0] dat_o;
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// Internal signal declarations
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reg [TMR_BITS_PP-1:0] tmr;
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reg [ROW_BITS_PP-1:0] row;
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reg [COLS_PP*(ROWS_PP-1)-1:0] shift_register;
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reg idle_state;
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wire keyscan_row_clk;
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wire end_of_scan;
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wire [ROWS_PP-1:0] row_output_binary;
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//--------------------------------------------------------------------------
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// Functions & Tasks
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//--------------------------------------------------------------------------
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function [ROWS_PP-1:0] one_low_among_z;
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input [ROW_BITS_PP-1:0] row;
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integer k;
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begin
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for (k=0; k<ROWS_PP; k=k+1)
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one_low_among_z[k] = (k == row)?1'b0:1'bZ;
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end
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endfunction
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//--------------------------------------------------------------------------
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// Module code
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// This is the inter-row timer. It advances the row count at a certain rate
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always @(posedge clk_i)
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begin
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if (rst_i || idle_state) tmr <= 0;
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else if (clk_en_i) tmr <= tmr + 1;
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end
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assign keyscan_row_clk = (clk_en_i && (tmr == TMR_CLKS_PP-1));
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// This is the row counter
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always @(posedge clk_i)
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begin
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if (rst_i || end_of_scan) row <= 0;
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else if (keyscan_row_clk) row <= row + 1;
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end // End of always block
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assign end_of_scan = ((row == ROWS_PP-1) && keyscan_row_clk);
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// This is the "idle_state" logic
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always @(posedge clk_i)
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begin
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if (rst_i) idle_state <= 1; // Begin in idle state
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else if (scan_i && idle_state) idle_state <= 0;
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else if (end_of_scan && ~scan_i) idle_state <= 1;
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end
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assign done_o = (end_of_scan || idle_state);
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// This is the shift register. Whenever the row count advances, this
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// shift register captures row data, except during "final_scan_row."
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// When "final_scan_row" is active, then that final row goes directly
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// to the output for storage.
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always @(posedge clk_i)
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begin
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if (keyscan_row_clk && ~end_of_scan)
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begin
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shift_register <= {shift_register,col_i};
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// Alternative coding
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//shift_register[COLS_PP*(ROWS_PP-1)-1:COLS_PP]
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// <= shift_register[COLS_PP*(ROWS_PP-2)-1:0];
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//shift_register[COLS_PP-1:0] <= col_i;
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end
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end
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// This is the bank of actual output registers. It captures the column info
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// during the final row, and also all of the other column info. stored during
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// previous row counts (i.e. what is stored in the shift register)
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always @(posedge clk_i)
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begin
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if (rst_i) dat_o <= 0;
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else if (keyscan_row_clk && end_of_scan) dat_o <= {shift_register,col_i};
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end
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// This is the row driver. It decodes the current row count into a "one low
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// of N" output. The rest of the N outputs are high-impedance (Z).
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assign row_o = one_low_among_z(row);
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endmodule
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