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<meta http-equiv="Content-Language" content="en-us">
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<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
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<meta name="GENERATOR" content="Microsoft FrontPage 4.0">
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<meta name="ProgId" content="FrontPage.Editor.Document">
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<title>A Little Bit about Alliance</title>
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<body bgcolor="#FFCCCC">
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<p align="center"><font face="Times New Roman" size="5">A Little Bit about
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Alliance</font></p>
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<p align="center"> </p>
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<p><font size="4"><b>A. Introduction</b></font></p>
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<p><font size="4">Alliance is a Computer Aided Design System for Very Large
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Scale Integrated Circuits (VLSI) design. Alliance is a non-commercial
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software developed by Équipe Achitecture des Systèmes et Micro-Électronique,
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Laboratoire d'Informatique de Paris 6,Université Pierre et Marie Curie,
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France. So, if you are interested in Alliance, you can get the software
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and more information at <a href="http://www-asim.lip6.fr">http://www-asim.lip6.fr</a>
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. We usually run this software under Linux Operating Systems (we use Red
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Hat Linux 6.2).</font></p>
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<font size="4">The ALLIANCE VHDL</font> is dedicated to digital
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synchronous circuits design, which is usually used for:
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<ul>
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<li><font size="4">logic simulation </font>
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<li><font size="4">logic synthesis </font>
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<li><font size="4">functional abstraction </font>
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<li><font size="4">formal proof</font> </li>
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</ul>
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<p><font size="4">The ALLIANCE VHDL is fully compatible with the IEEE VHDL
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standard Ref. 1076 (1987). That means that a VHDL description using the ALLIANCE
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subset can be simulated with any full-VHDL commercial compiler-simulator.</font></p>
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<p><font size="4">The VHDL description of a circuit is made of two separate
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parts: the external view and the internal view.</font>
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<p><font size="4">The external view defines the name of the circuit and its
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interface. The interface of a circuit is a list of ports. Each port is specified
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by its name, its mode, its type, its constraint for an array and, its kind.</font>
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<p><font size="4">The mode of a port depends only on the manner the port is used
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inside the circuit (in the internal view of the circuit). If the value of a port
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is to be read in the view of the description, the port must be declared with the
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mode <code>IN</code>. If the value of a port is to be written by the internal
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view, the port must be declared with the mode <code>OUT</code>. If both above
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conditions are satisfied the port must be declared with the mode <code>INOUT</code>.</font>
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<font size="4">Only structural and behavioural data flow are supported as
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internal view.</font>
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<p><font size="4">A circuit, a subcircuit, or a cell can have two different
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descriptions:</font>
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<ul>
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<li><font size="4">a structural view may be defined in a file with a <code>.vst</code>
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extension </font>
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<li><font size="4">a behavioural data flow description may be defined in a
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file with a <code>.vbe</code> extension.</font></li>
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</ul>
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<p> </p>
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<p><font size="4"><b>B. Starting Using Alliance</b></font></p>
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<p><font size="4">We can start using Alliance by linking our workspace to the
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source of Alliance by typing :</font></p>
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<p> <font size="4">
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<b>source /home/cad/alliance/share/etc/alc_env.csh</b></font></p>
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<p><font size="4">here we assume that the Alliance is located in directory
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/home/cad.</font></p>
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<p><font size="4">The next step is to set the environment of Alliance. We
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usually use logic gates from <b>sclib</b> to develop a circuit. So, we
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must set the environment by typing :<br>
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</font></p>
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<p> <font size="4"><b>setenv
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MBK_CATA_LIB .:/home/cad/alliance/archi/Linux/cells/sclib</b></font></p>
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<p><font size="4">We must know the symbolic name of gate that we use by seeing
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manual of <b>sclib</b>. To see manual of all about command we want to know, we
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can type </font></p>
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<p> <font size="4">
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<b>man name_of_command </b></font></p>
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<p><font size="4">After that, we can start our design by typing the source code
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in the text editor. Our design can be from behavioural data flow
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description or logic circuit description. We can write our comment like
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this :</font></p>
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<p> <font size="4">
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/* our_comment */</font></p>
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<p><font size="4">If our design comes from behavioural data flow description, we
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save it with a <b>.vbe</b> extension. You can see examples of
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behavioural D-Flip Flop design <a href="dflipflop.shtml">here</a>. </font></p>
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<p><font size="4">If our design comes from logic circuit description, we save it
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with a <b>.c</b> extension.</font> <font size="4">In
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order to write this file, we must follow the syntax below :</font></p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">/*<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
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</span>genlib.h is required for all genlib programs.<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
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</span>it defines the set of functions we will use for schematic capture<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">*/</p>
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<p>#include <genlib.h><br>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">/*<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
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</span>decoder.c is to become the `core' executable program. So we must<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
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</span>define a main procedure main()<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">*/<o:p>
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</o:p>
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</p>
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<p>main()<br>
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{<br>
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DEF_LOFIG("decoder"); /* decoder.c is our file
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name */<br>
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</p>
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<p style="margin: 0">/* define inputs and outputs of our system */</p>
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<p class="MsoNormal" style="margin: 0"> </p>
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<p class="MsoNormal" style="margin: 0">/*<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin: 0"><span style="mso-spacerun: yes">
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</span>We start with the input terminals.<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin: 0"><span style="mso-spacerun: yes">
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</span>Only signals and connectors can be vectorized.<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin: 0">*/<o:p>
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</o:p>
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</p>
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<p style="word-spacing: 0; margin: 0">LOCON("x", IN, "x" );
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/* define input */<br>
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LOCON("res", IN, "res" );
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/* define reset input, if we need it */<br>
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LOCON("ck", IN, "ck" );
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/* define clock input */</p>
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<p style="word-spacing: 0; margin: 0">LOCON("z", INOUT, "z"
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); /* define an output of a gate
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but acts as input of another gate */</p>
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<p style="word-spacing: 0; margin: 0"> </p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">/*<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
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</span>Then,<span style="mso-spacerun: yes"> </span>the output terminals.<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">*/<o:p>
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</o:p>
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</p>
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<p style="word-spacing: 0; margin: 0"><br>
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LOCON("y[0:1]", OUT, "y[0:1]" );
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/* define output consists of 2
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bits*/</p>
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<p style="word-spacing: 0; margin: 0"> </p>
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<p style="word-spacing: 0; margin: 0"> </p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">/*<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
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</span>Then the supplies.<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
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</span>They are inputs, but we like them better at the end of the<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
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</span>description.<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">*/<o:p>
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</o:p>
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</p>
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<p style="word-spacing: 0; margin: 0">LOCON("vdd", IN, "vdd"
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); /* define vdd input */<br>
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LOCON("vss", IN, "vss" );
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/* define vss input */<br>
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<br>
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....</p>
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<p style="word-spacing: 0; margin: 0"> </p>
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<p style="word-spacing: 0; margin: 0">/* define all components that we use to
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develop our system */</p>
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<p style="word-spacing: 0; margin: 0"> </p>
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<p style="word-spacing: 0; margin: 0">LOINS("a2_y", "a1",
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"x", "m", "z", "vdd", "vss",0);</p>
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<p style="word-spacing: 0; margin: 0"> </p>
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<p style="word-spacing: 0; margin: 0">/* a2_y is a simbolic name for 2
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inputs <b>and gate</b> */</p>
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<p style="word-spacing: 0; margin: 0">/*<b> </b>a1 is our given name for
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this component where there must be no same name in<b> </b>the same file */</p>
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<p style="word-spacing: 0; margin: 0">/* x and m is inputs of a1 */</p>
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<p style="word-spacing: 0; margin: 0">/* z is the output of a1 */</p>
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<p style="word-spacing: 0; margin: 0"> </p>
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<p style="word-spacing: 0; margin: 0">....</p>
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<p style="word-spacing: 0; margin: 0"> </p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">SAVE_LOFIG();<o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
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</span>exit(0);<span style="mso-spacerun: yes">
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</span>/* necessary for the proper run of the Makefile */ <o:p>
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</o:p>
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</p>
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<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">}<span style="mso-spacerun: yes">
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</span><o:p>
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</o:p>
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</p>
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<p style="word-spacing: 0; margin: 0"> </p>
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<p style="word-spacing: 0; margin: 0"><font size="4"><a href="counter.shtml">Here</a>
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we can see the example <b>.c</b> file of 4-bit counter.</font></p>
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<p style="word-spacing: 0; margin: 0"> </p>
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<p style="word-spacing: 0; margin: 0"><font size="4"><b>C. Basic Alliance
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Tools</b></font></p>
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<p style="word-spacing: 0; margin: 0"> </p>
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<p style="word-spacing: 0; margin: 0"><font size="4">After that, we </font><font size="4">are
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now ready to actually design the chip and use the Alliance tools. The design
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flow for this little example is composed of 5 main steps:</font></p>
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<ul>
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<li>
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<p style="margin-top: 0; margin-bottom: 0"><font size="4">behavioral capture
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and simulation</font></li>
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<li>
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<p style="margin-top: 0; margin-bottom: 0"><font size="4">netlist capture
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and validation</font></li>
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<li>
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<p style="margin-top: 0; margin-bottom: 0"><font size="4">physical layout
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generation</font></li>
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<li>
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<p style="margin-top: 0; margin-bottom: 0"><font size="4">design validation</font></li>
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<li>
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<p style="margin-top: 0; margin-bottom: 0"><font size="4">symbolic to real
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conversion.</font></li>
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</ul>
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<p><font size="4">First of all, we must make a structural file (<b>.vst</b>).
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We can get structural view from our behavioural data flow description (<b>.vbe</b>)
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file or from our <b>.c</b> file. Here are the basic Alliance tools :</font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(i)<span style="mso-spacerun: yes">
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</span>genlib</font></b></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">By
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using this tool, we can change our logic circuit description file (<b>.c</b>)
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into structural file (<b>.vst</b>) which more useful in next process. <b><O:P>
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</b>The command is :</font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">
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|
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<b> </b>
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<b>genlib .c_file_name</O:P>
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</b></font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(ii)<span style="mso-spacerun: yes">
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</span>scmap<O:P>
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</font></b></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">Our
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behavioural data flow description file (<b>.vbe</b>) can be changed into
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structural file (<b>.vst</b>) by using this tool. The command is :<br>
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</font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4"><b>
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scmap .vbe_ file_name .vst_file_name
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</b></font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">We
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can see the structural file (<b>.vst</b>) generated from the previous
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behavioural D-Flip Flop design <a href="struct.shtml">here</a>.<b></O:P>
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</b></font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(iii)
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asimut </font></b></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">This
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tool is usually used to simulate our design by giving some inputs. We can
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see simulation results, which can be compared to our expected outputs. We
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must create a test pattern file (<b>.pat</b>) contains some inputs we will
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use in the simulation. You can see the example of test pattern file <a href="test.shtml">here</a>.
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The command is :</font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4"><br>
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<b> asimut .vst_file_name test_pattern_file_name
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simulation_results_file_name</b> <b><O:P>
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</O:P>
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</b></font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(iv)
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xsch<O:P>
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</O:P>
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</font></b></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">We
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can see logic circuit of our structural file by using this tools.</font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(v)
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xpat<O:P>
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</O:P>
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</font></b></p>
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<font size="4">We can see timing diagrams of test pattern file (<b>.pat</b>) and our asimut
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result file (<b>.pat</b>) by using <b>xpat</b> tool.</font>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(vi)
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scr<O:P>
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</O:P>
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</font></b></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">Our
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structural file can be extracted into symbolic layout using <b>scr</b>.
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The command is :<br>
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<b>scr -sclib -p -r file_name</b></font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">This
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symbolic layout result (<b>.ap</b>) can be viewed by <b>graal</b> tool.<b><O:P>
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</O:P>
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</b></font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(vii)
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s2r</font></b></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">Our
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symbolic layout can be changed into real layout by using <b>s2r</b>. The
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command is :<br>
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<b>
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s2r file_name</b> </font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">This
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real layout (<b>.cif</b>) can be viewed by using <b>dreal</b> tool.</font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(viii) <span style="mso-spacerun: yes">
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</span>lynx<O:P>
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</O:P>
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</font></b></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">Our
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real layout can be changed into new structural file (<b>.al</b>) by using <b>lynx</b>.
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First, we must set the environmet by the command :</font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4"><b> </b>
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<b>setenv MBK_OUT_LO al</b></font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">then
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we type the command :</font></p>
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<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"> <font size="4">
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| 331 |
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<b>lynx -v .ap_file_name output_file_name -f</b></font></p>
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| 332 |
|
|
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">After
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| 333 |
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this, we can do simulation post-layout on the old (<b>.vst</b>) and new (<b>.al</b>)
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| 334 |
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structural file by using <b>lvx</b>. The command is : </font></p>
|
| 335 |
|
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<p><b><font size="4">
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| 336 |
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lvx vst al .vst_file_name .al_file_name</font></b></p>
|
| 337 |
|
|
<p><font size="4">Another way to compare the result is using <b>asimut</b>.
|
| 338 |
|
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We can simulate the new structural file (<b>.al</b>) with the previous test
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| 339 |
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pattern file using asimut. But first, we must set the environment :<br>
|
| 340 |
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</font></p>
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| 341 |
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<p><b> </b><font size="4"><b>
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| 342 |
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setenv MBK_IN_LO al</b></font></p>
|
| 343 |
|
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<p><font size="4">then using <b>asimut</b> :</font></p>
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| 344 |
|
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<p align="center"><font size="4"><b>
|
| 345 |
|
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asimut .al_file_name testpattern_file_name result_file_name </b></font></p>
|
| 346 |
|
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<p><font size="4">After that we can compare the new simulation result with the
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| 347 |
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|
previous simulation result. We expect to get the same result.</font></p>
|
| 348 |
|
|
|
| 349 |
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<p> </p>
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| 350 |
|
|
|
| 351 |
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<p><font size="4">To know more about Alliance and find tutorials, you can
|
| 352 |
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visit <a href="http://www-asim.lip6.fr">http://www-asim.lip6.fr</a></font></p>
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| 353 |
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|
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| 354 |
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</body>
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| 355 |
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</html>
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