| 1 |
6 |
root |
<html>
|
| 2 |
|
|
<head>
|
| 3 |
|
|
<title>OPENCORES.ORG</title>
|
| 4 |
|
|
<META NAME="keywords" CONTENT="cores, VHDL, Verilog HDL, ASIC, Synthesizable,
|
| 5 |
|
|
standard cell, IP, Intellectual Property, 32-bit RISC, UART, PCI, SDRAM,
|
| 6 |
|
|
full custom, system on a chip, SOC, reusable, design, development, synthesis,
|
| 7 |
|
|
designs, developers, C, Linux, eCos, open, free, open source cores, RTL code,
|
| 8 |
|
|
system-on-a-chip, circuits, digital, GNU, GPL, core, controller, processor,
|
| 9 |
|
|
system design, chip design, EDA, design methodology, design tools, ASICs, programmable logic,
|
| 10 |
|
|
FPGA's, PLDs, CPLDs, verification, Synthesis, HDL, Simulation, IC design software,
|
| 11 |
|
|
semiconductor design, integrated circuits, system designs, chip designs, EDAs,
|
| 12 |
|
|
design methodologies, design tool, ASIC, programmable logics, FPGA, PLD, CPLD, Synthesis,
|
| 13 |
|
|
circuit, Synopsys, system design, chip design, programmable logic, FPGA's, PLDs,
|
| 14 |
|
|
CPLDs, verification, Simulation">
|
| 15 |
|
|
<META NAME="description" CONTENT="OPENCORES.ORG endorses development and hosts
|
| 16 |
|
|
a repository of free, open source IP cores (chip designs, System-on-a-Chip) and
|
| 17 |
|
|
supplemental boards.">
|
| 18 |
|
|
</head>
|
| 19 |
|
|
|
| 20 |
|
|
<body bgcolor=#ffffff>
|
| 21 |
|
|
|
| 22 |
|
|
<table width="100%" cellspacing=5 cellpadding=0 border=0>
|
| 23 |
|
|
<tr valign="top"><td>
|
| 24 |
|
|
<center>
|
| 25 |
|
|
<table cellspacing=0 cellpadding=5 width="100%" valign="top" border=0>
|
| 26 |
|
|
<tr valign="top"><td bgcolor=#f0f0f0 valign="top">
|
| 27 |
|
|
<center><font size=+3><b>OPENCORES.ORG</b></font>
|
| 28 |
|
|
<br><font size=-4><font color=#ffffff>.</font></font>
|
| 29 |
|
|
<br>
|
| 30 |
|
|
</center>
|
| 31 |
|
|
|
| 32 |
|
|
</td></tr></table>
|
| 33 |
|
|
|
| 34 |
|
|
|
| 35 |
|
|
</center>
|
| 36 |
|
|
|
| 37 |
|
|
|
| 38 |
|
|
</td></tr>
|
| 39 |
|
|
|
| 40 |
|
|
<tr valign="top"><td>
|
| 41 |
|
|
<table border=0 cellspacing=0 cellpadding=5 width="100%"><tr valign="top"><td bgcolor="#f8f8f0">
|
| 42 |
|
|
|
| 43 |
|
|
|
| 44 |
|
|
|
| 45 |
|
|
</td>
|
| 46 |
|
|
<td valign="top">
|
| 47 |
|
|
<table cellpadding=5><tr><td valign="top">
|
| 48 |
|
|
|
| 49 |
|
|
<font SIZE="2">-- VHDL structural description generated from `ram`
|
| 50 |
|
|
<p>-- date : Tue Feb 20 23:00:09 2001</p>
|
| 51 |
|
|
<p> </p>
|
| 52 |
|
|
<p>-- Entity Declaration</p>
|
| 53 |
|
|
<p>ENTITY ram IS</p>
|
| 54 |
|
|
<p>PORT (</p>
|
| 55 |
|
|
<p>rws : in BIT; -- rws</p>
|
| 56 |
|
|
<p>cs : in BIT; -- cs</p>
|
| 57 |
|
|
<p>res : in BIT; -- res</p>
|
| 58 |
|
|
<p>c : in BIT_VECTOR (0 TO 15); -- c</p>
|
| 59 |
|
|
<p>io0 : inout BIT; -- io0</p>
|
| 60 |
|
|
<p>io1 : inout BIT; -- io1</p>
|
| 61 |
|
|
<p>io2 : inout BIT; -- io2</p>
|
| 62 |
|
|
<p>io3 : inout BIT; -- io3</p>
|
| 63 |
|
|
<p>io4 : inout BIT; -- io4</p>
|
| 64 |
|
|
<p>io5 : inout BIT; -- io5</p>
|
| 65 |
|
|
<p>io6 : inout BIT; -- io6</p>
|
| 66 |
|
|
<p>io7 : inout BIT; -- io7</p>
|
| 67 |
|
|
<p>vdd : in BIT; -- vdd</p>
|
| 68 |
|
|
<p>vss : in BIT -- vss</p>
|
| 69 |
|
|
<p>);</p>
|
| 70 |
|
|
<p>END ram;</p>
|
| 71 |
|
|
<p>-- Architecture Declaration</p>
|
| 72 |
|
|
<p>ARCHITECTURE VST OF ram IS</p>
|
| 73 |
|
|
<p>COMPONENT a2_y</p>
|
| 74 |
|
|
<p>port (</p>
|
| 75 |
|
|
<p>i0 : in BIT; -- i0</p>
|
| 76 |
|
|
<p>i1 : in BIT; -- i1</p>
|
| 77 |
|
|
<p>t : out BIT; -- t</p>
|
| 78 |
|
|
<p>vdd : in BIT; -- vdd</p>
|
| 79 |
|
|
<p>vss : in BIT -- vss</p>
|
| 80 |
|
|
<p>);</p>
|
| 81 |
|
|
<p>END COMPONENT;</p>
|
| 82 |
|
|
<p>COMPONENT mc</p>
|
| 83 |
|
|
<p>port (</p>
|
| 84 |
|
|
<p>x : in BIT; -- x</p>
|
| 85 |
|
|
<p>res : in BIT; -- res</p>
|
| 86 |
|
|
<p>rowsel : in BIT; -- rowsel</p>
|
| 87 |
|
|
<p>wren : in BIT; -- wren</p>
|
| 88 |
|
|
<p>y : out BIT; -- y</p>
|
| 89 |
|
|
<p>vdd : in BIT; -- vdd</p>
|
| 90 |
|
|
<p>vss : in BIT -- vss</p>
|
| 91 |
|
|
<p>);</p>
|
| 92 |
|
|
<p>END COMPONENT;</p>
|
| 93 |
|
|
<p>COMPONENT p1_y</p>
|
| 94 |
|
|
<p>port (</p>
|
| 95 |
|
|
<p>i : in BIT; -- i</p>
|
| 96 |
|
|
<p>t : out BIT; -- t</p>
|
| 97 |
|
|
<p>vdd : in BIT; -- vdd</p>
|
| 98 |
|
|
<p>vss : in BIT -- vss</p>
|
| 99 |
|
|
<p>);</p>
|
| 100 |
|
|
<p>END COMPONENT;</p>
|
| 101 |
|
|
<p>SIGNAL in0 : BIT; -- in0</p>
|
| 102 |
|
|
<p>SIGNAL in1 : BIT; -- in1</p>
|
| 103 |
|
|
<p>SIGNAL in2 : BIT; -- in2</p>
|
| 104 |
|
|
<p>SIGNAL in3 : BIT; -- in3</p>
|
| 105 |
|
|
<p>SIGNAL in4 : BIT; -- in4</p>
|
| 106 |
|
|
<p>SIGNAL in5 : BIT; -- in5</p>
|
| 107 |
|
|
<p>SIGNAL in6 : BIT; -- in6</p>
|
| 108 |
|
|
<p>SIGNAL in7 : BIT; -- in7</p>
|
| 109 |
|
|
<p>SIGNAL q0 : BIT; -- q0</p>
|
| 110 |
|
|
<p>SIGNAL q1 : BIT; -- q1</p>
|
| 111 |
|
|
<p>SIGNAL q2 : BIT; -- q2</p>
|
| 112 |
|
|
<p>SIGNAL q3 : BIT; -- q3</p>
|
| 113 |
|
|
<p>SIGNAL q4 : BIT; -- q4</p>
|
| 114 |
|
|
<p>SIGNAL q5 : BIT; -- q5</p>
|
| 115 |
|
|
<p>SIGNAL q6 : BIT; -- q6</p>
|
| 116 |
|
|
<p>SIGNAL q7 : BIT; -- q7</p>
|
| 117 |
|
|
<p>SIGNAL wren : BIT; -- wren</p>
|
| 118 |
|
|
<p>BEGIN</p>
|
| 119 |
|
|
<p>and1 : a2_y</p>
|
| 120 |
|
|
<p>PORT MAP (</p>
|
| 121 |
|
|
<p>vss => vss,</p>
|
| 122 |
|
|
<p>vdd => vdd,</p>
|
| 123 |
|
|
<p>t => wren,</p>
|
| 124 |
|
|
<p>i1 => cs,</p>
|
| 125 |
|
|
<p>i0 => rws);</p>
|
| 126 |
|
|
<p>bufi7 : p1_y</p>
|
| 127 |
|
|
<p>PORT MAP (</p>
|
| 128 |
|
|
<p>vss => vss,</p>
|
| 129 |
|
|
<p>vdd => vdd,</p>
|
| 130 |
|
|
<p>t => in7,</p>
|
| 131 |
|
|
<p>i => io7);</p>
|
| 132 |
|
|
<p>bufi6 : p1_y</p>
|
| 133 |
|
|
<p>PORT MAP (</p>
|
| 134 |
|
|
<p>vss => vss,</p>
|
| 135 |
|
|
<p>vdd => vdd,</p>
|
| 136 |
|
|
<p>t => in6,</p>
|
| 137 |
|
|
<p>i => io6);</p>
|
| 138 |
|
|
<p>bufi5 : p1_y</p>
|
| 139 |
|
|
<p>PORT MAP (</p>
|
| 140 |
|
|
<p>vss => vss,</p>
|
| 141 |
|
|
<p>vdd => vdd,</p>
|
| 142 |
|
|
<p>t => in5,</p>
|
| 143 |
|
|
<p>i => io5);</p>
|
| 144 |
|
|
<p>bufi4 : p1_y</p>
|
| 145 |
|
|
<p>PORT MAP (</p>
|
| 146 |
|
|
<p>vss => vss,</p>
|
| 147 |
|
|
<p>vdd => vdd,</p>
|
| 148 |
|
|
<p>t => in4,</p>
|
| 149 |
|
|
<p>i => io4);</p>
|
| 150 |
|
|
<p>bufi3 : p1_y</p>
|
| 151 |
|
|
<p>PORT MAP (</p>
|
| 152 |
|
|
<p>vss => vss,</p>
|
| 153 |
|
|
<p>vdd => vdd,</p>
|
| 154 |
|
|
<p>t => in3,</p>
|
| 155 |
|
|
<p>i => io3);</p>
|
| 156 |
|
|
<p>bufi2 : p1_y</p>
|
| 157 |
|
|
<p>PORT MAP (</p>
|
| 158 |
|
|
<p>vss => vss,</p>
|
| 159 |
|
|
<p>vdd => vdd,</p>
|
| 160 |
|
|
<p>t => in2,</p>
|
| 161 |
|
|
<p>i => io2);</p>
|
| 162 |
|
|
<p>bufi1 : p1_y</p>
|
| 163 |
|
|
<p>PORT MAP (</p>
|
| 164 |
|
|
<p>vss => vss,</p>
|
| 165 |
|
|
<p>vdd => vdd,</p>
|
| 166 |
|
|
<p>t => in1,</p>
|
| 167 |
|
|
<p>i => io1);</p>
|
| 168 |
|
|
<p>bufi0 : p1_y</p>
|
| 169 |
|
|
<p>PORT MAP (</p>
|
| 170 |
|
|
<p>vss => vss,</p>
|
| 171 |
|
|
<p>vdd => vdd,</p>
|
| 172 |
|
|
<p>t => in0,</p>
|
| 173 |
|
|
<p>i => io0);</p>
|
| 174 |
|
|
<p>mc07 : mc</p>
|
| 175 |
|
|
<p>PORT MAP (</p>
|
| 176 |
|
|
<p>vss => vss,</p>
|
| 177 |
|
|
<p>vdd => vdd,</p>
|
| 178 |
|
|
<p>y => q7,</p>
|
| 179 |
|
|
<p>wren => res,</p>
|
| 180 |
|
|
<p>rowsel => in7,</p>
|
| 181 |
|
|
<p>res => wren,</p>
|
| 182 |
|
|
<p>x => c(0));</p>
|
| 183 |
|
|
<p>mc06 : mc</p>
|
| 184 |
|
|
<p>PORT MAP (</p>
|
| 185 |
|
|
<p>vss => vss,</p>
|
| 186 |
|
|
<p>vdd => vdd,</p>
|
| 187 |
|
|
<p>y => q6,</p>
|
| 188 |
|
|
<p>wren => res,</p>
|
| 189 |
|
|
<p>rowsel => in6,</p>
|
| 190 |
|
|
<p>res => wren,</p>
|
| 191 |
|
|
<p>x => c(0));</p>
|
| 192 |
|
|
<p>mc05 : mc</p>
|
| 193 |
|
|
<p>PORT MAP (</p>
|
| 194 |
|
|
<p>vss => vss,</p>
|
| 195 |
|
|
<p>vdd => vdd,</p>
|
| 196 |
|
|
<p>y => q5,</p>
|
| 197 |
|
|
<p>wren => res,</p>
|
| 198 |
|
|
<p>rowsel => in5,</p>
|
| 199 |
|
|
<p>res => wren,</p>
|
| 200 |
|
|
<p>x => c(0));</p>
|
| 201 |
|
|
<p>mc04 : mc</p>
|
| 202 |
|
|
<p>PORT MAP (</p>
|
| 203 |
|
|
<p>vss => vss,</p>
|
| 204 |
|
|
<p>vdd => vdd,</p>
|
| 205 |
|
|
<p>y => q4,</p>
|
| 206 |
|
|
<p>wren => res,</p>
|
| 207 |
|
|
<p>rowsel => in4,</p>
|
| 208 |
|
|
<p>res => wren,</p>
|
| 209 |
|
|
<p>x => c(0));</p>
|
| 210 |
|
|
<p>mc03 : mc</p>
|
| 211 |
|
|
<p>PORT MAP (</p>
|
| 212 |
|
|
<p>vss => vss,</p>
|
| 213 |
|
|
<p>vdd => vdd,</p>
|
| 214 |
|
|
<p>y => q3,</p>
|
| 215 |
|
|
<p>wren => res,</p>
|
| 216 |
|
|
<p>rowsel => in3,</p>
|
| 217 |
|
|
<p>res => wren,</p>
|
| 218 |
|
|
<p>x => c(0));</p>
|
| 219 |
|
|
<p>mc02 : mc</p>
|
| 220 |
|
|
<p>PORT MAP (</p>
|
| 221 |
|
|
<p>vss => vss,</p>
|
| 222 |
|
|
<p>vdd => vdd,</p>
|
| 223 |
|
|
<p>y => q2,</p>
|
| 224 |
|
|
<p>wren => res,</p>
|
| 225 |
|
|
<p>rowsel => in2,</p>
|
| 226 |
|
|
<p>res => wren,</p>
|
| 227 |
|
|
<p>x => c(0));</p>
|
| 228 |
|
|
<p>mc01 : mc</p>
|
| 229 |
|
|
<p>PORT MAP (</p>
|
| 230 |
|
|
<p>vss => vss,</p>
|
| 231 |
|
|
<p>vdd => vdd,</p>
|
| 232 |
|
|
<p>y => q1,</p>
|
| 233 |
|
|
<p>wren => res,</p>
|
| 234 |
|
|
<p>rowsel => in1,</p>
|
| 235 |
|
|
<p>res => wren,</p>
|
| 236 |
|
|
<p>x => c(0));</p>
|
| 237 |
|
|
<p>mc00 : mc</p>
|
| 238 |
|
|
<p>PORT MAP (</p>
|
| 239 |
|
|
<p>vss => vss,</p>
|
| 240 |
|
|
<p>vdd => vdd,</p>
|
| 241 |
|
|
<p>y => q0,</p>
|
| 242 |
|
|
<p>wren => res,</p>
|
| 243 |
|
|
<p>rowsel => in0,</p>
|
| 244 |
|
|
<p>res => wren,</p>
|
| 245 |
|
|
<p>x => c(0));</p>
|
| 246 |
|
|
<p>mc17 : mc</p>
|
| 247 |
|
|
<p>PORT MAP (</p>
|
| 248 |
|
|
<p>vss => vss,</p>
|
| 249 |
|
|
<p>vdd => vdd,</p>
|
| 250 |
|
|
<p>y => q7,</p>
|
| 251 |
|
|
<p>wren => res,</p>
|
| 252 |
|
|
<p>rowsel => in7,</p>
|
| 253 |
|
|
<p>res => wren,</p>
|
| 254 |
|
|
<p>x => c(1));</p>
|
| 255 |
|
|
<p>mc16 : mc</p>
|
| 256 |
|
|
<p>PORT MAP (</p>
|
| 257 |
|
|
<p>vss => vss,</p>
|
| 258 |
|
|
<p>vdd => vdd,</p>
|
| 259 |
|
|
<p>y => q6,</p>
|
| 260 |
|
|
<p>wren => res,</p>
|
| 261 |
|
|
<p>rowsel => in6,</p>
|
| 262 |
|
|
<p>res => wren,</p>
|
| 263 |
|
|
<p>x => c(1));</p>
|
| 264 |
|
|
<p>mc15 : mc</p>
|
| 265 |
|
|
<p>PORT MAP (</p>
|
| 266 |
|
|
<p>vss => vss,</p>
|
| 267 |
|
|
<p>vdd => vdd,</p>
|
| 268 |
|
|
<p>y => q5,</p>
|
| 269 |
|
|
<p>wren => res,</p>
|
| 270 |
|
|
<p>rowsel => in5,</p>
|
| 271 |
|
|
<p>res => wren,</p>
|
| 272 |
|
|
<p>x => c(1));</p>
|
| 273 |
|
|
<p>mc14 : mc</p>
|
| 274 |
|
|
<p>PORT MAP (</p>
|
| 275 |
|
|
<p>vss => vss,</p>
|
| 276 |
|
|
<p>vdd => vdd,</p>
|
| 277 |
|
|
<p>y => q4,</p>
|
| 278 |
|
|
<p>wren => res,</p>
|
| 279 |
|
|
<p>rowsel => in4,</p>
|
| 280 |
|
|
<p>res => wren,</p>
|
| 281 |
|
|
<p>x => c(1));</p>
|
| 282 |
|
|
<p>mc13 : mc</p>
|
| 283 |
|
|
<p>PORT MAP (</p>
|
| 284 |
|
|
<p>vss => vss,</p>
|
| 285 |
|
|
<p>vdd => vdd,</p>
|
| 286 |
|
|
<p>y => q3,</p>
|
| 287 |
|
|
<p>wren => res,</p>
|
| 288 |
|
|
<p>rowsel => in3,</p>
|
| 289 |
|
|
<p>res => wren,</p>
|
| 290 |
|
|
<p>x => c(1));</p>
|
| 291 |
|
|
<p>mc12 : mc</p>
|
| 292 |
|
|
<p>PORT MAP (</p>
|
| 293 |
|
|
<p>vss => vss,</p>
|
| 294 |
|
|
<p>vdd => vdd,</p>
|
| 295 |
|
|
<p>y => q2,</p>
|
| 296 |
|
|
<p>wren => res,</p>
|
| 297 |
|
|
<p>rowsel => in2,</p>
|
| 298 |
|
|
<p>res => wren,</p>
|
| 299 |
|
|
<p>x => c(1));</p>
|
| 300 |
|
|
<p>mc11 : mc</p>
|
| 301 |
|
|
<p>PORT MAP (</p>
|
| 302 |
|
|
<p>vss => vss,</p>
|
| 303 |
|
|
<p>vdd => vdd,</p>
|
| 304 |
|
|
<p>y => q1,</p>
|
| 305 |
|
|
<p>wren => res,</p>
|
| 306 |
|
|
<p>rowsel => in1,</p>
|
| 307 |
|
|
<p>res => wren,</p>
|
| 308 |
|
|
<p>x => c(1));</p>
|
| 309 |
|
|
<p>mc10 : mc</p>
|
| 310 |
|
|
<p>PORT MAP (</p>
|
| 311 |
|
|
<p>vss => vss,</p>
|
| 312 |
|
|
<p>vdd => vdd,</p>
|
| 313 |
|
|
<p>y => q0,</p>
|
| 314 |
|
|
<p>wren => res,</p>
|
| 315 |
|
|
<p>rowsel => in0,</p>
|
| 316 |
|
|
<p>res => wren,</p>
|
| 317 |
|
|
<p>x => c(1));</p>
|
| 318 |
|
|
<p>mc27 : mc</p>
|
| 319 |
|
|
<p>PORT MAP (</p>
|
| 320 |
|
|
<p>vss => vss,</p>
|
| 321 |
|
|
<p>vdd => vdd,</p>
|
| 322 |
|
|
<p>y => q7,</p>
|
| 323 |
|
|
<p>wren => res,</p>
|
| 324 |
|
|
<p>rowsel => in7,</p>
|
| 325 |
|
|
<p>res => wren,</p>
|
| 326 |
|
|
<p>x => c(2));</p>
|
| 327 |
|
|
<p>mc26 : mc</p>
|
| 328 |
|
|
<p>PORT MAP (</p>
|
| 329 |
|
|
<p>vss => vss,</p>
|
| 330 |
|
|
<p>vdd => vdd,</p>
|
| 331 |
|
|
<p>y => q6,</p>
|
| 332 |
|
|
<p>wren => res,</p>
|
| 333 |
|
|
<p>rowsel => in6,</p>
|
| 334 |
|
|
<p>res => wren,</p>
|
| 335 |
|
|
<p>x => c(2));</p>
|
| 336 |
|
|
<p>mc25 : mc</p>
|
| 337 |
|
|
<p>PORT MAP (</p>
|
| 338 |
|
|
<p>vss => vss,</p>
|
| 339 |
|
|
<p>vdd => vdd,</p>
|
| 340 |
|
|
<p>y => q5,</p>
|
| 341 |
|
|
<p>wren => res,</p>
|
| 342 |
|
|
<p>rowsel => in5,</p>
|
| 343 |
|
|
<p>res => wren,</p>
|
| 344 |
|
|
<p>x => c(2));</p>
|
| 345 |
|
|
<p>mc24 : mc</p>
|
| 346 |
|
|
<p>PORT MAP (</p>
|
| 347 |
|
|
<p>vss => vss,</p>
|
| 348 |
|
|
<p>vdd => vdd,</p>
|
| 349 |
|
|
<p>y => q4,</p>
|
| 350 |
|
|
<p>wren => res,</p>
|
| 351 |
|
|
<p>rowsel => in4,</p>
|
| 352 |
|
|
<p>res => wren,</p>
|
| 353 |
|
|
<p>x => c(2));</p>
|
| 354 |
|
|
<p>mc23 : mc</p>
|
| 355 |
|
|
<p>PORT MAP (</p>
|
| 356 |
|
|
<p>vss => vss,</p>
|
| 357 |
|
|
<p>vdd => vdd,</p>
|
| 358 |
|
|
<p>y => q3,</p>
|
| 359 |
|
|
<p>wren => res,</p>
|
| 360 |
|
|
<p>rowsel => in3,</p>
|
| 361 |
|
|
<p>res => wren,</p>
|
| 362 |
|
|
<p>x => c(2));</p>
|
| 363 |
|
|
<p>mc22 : mc</p>
|
| 364 |
|
|
<p>PORT MAP (</p>
|
| 365 |
|
|
<p>vss => vss,</p>
|
| 366 |
|
|
<p>vdd => vdd,</p>
|
| 367 |
|
|
<p>y => q2,</p>
|
| 368 |
|
|
<p>wren => res,</p>
|
| 369 |
|
|
<p>rowsel => in2,</p>
|
| 370 |
|
|
<p>res => wren,</p>
|
| 371 |
|
|
<p>x => c(2));</p>
|
| 372 |
|
|
<p>mc21 : mc</p>
|
| 373 |
|
|
<p>PORT MAP (</p>
|
| 374 |
|
|
<p>vss => vss,</p>
|
| 375 |
|
|
<p>vdd => vdd,</p>
|
| 376 |
|
|
<p>y => q1,</p>
|
| 377 |
|
|
<p>wren => res,</p>
|
| 378 |
|
|
<p>rowsel => in1,</p>
|
| 379 |
|
|
<p>res => wren,</p>
|
| 380 |
|
|
<p>x => c(2));</p>
|
| 381 |
|
|
<p>mc20 : mc</p>
|
| 382 |
|
|
<p>PORT MAP (</p>
|
| 383 |
|
|
<p>vss => vss,</p>
|
| 384 |
|
|
<p>vdd => vdd,</p>
|
| 385 |
|
|
<p>y => q0,</p>
|
| 386 |
|
|
<p>wren => res,</p>
|
| 387 |
|
|
<p>rowsel => in0,</p>
|
| 388 |
|
|
<p>res => wren,</p>
|
| 389 |
|
|
<p>x => c(2));</p>
|
| 390 |
|
|
<p>mc37 : mc</p>
|
| 391 |
|
|
<p>PORT MAP (</p>
|
| 392 |
|
|
<p>vss => vss,</p>
|
| 393 |
|
|
<p>vdd => vdd,</p>
|
| 394 |
|
|
<p>y => q7,</p>
|
| 395 |
|
|
<p>wren => res,</p>
|
| 396 |
|
|
<p>rowsel => in7,</p>
|
| 397 |
|
|
<p>res => wren,</p>
|
| 398 |
|
|
<p>x => c(3));</p>
|
| 399 |
|
|
<p>mc36 : mc</p>
|
| 400 |
|
|
<p>PORT MAP (</p>
|
| 401 |
|
|
<p>vss => vss,</p>
|
| 402 |
|
|
<p>vdd => vdd,</p>
|
| 403 |
|
|
<p>y => q6,</p>
|
| 404 |
|
|
<p>wren => res,</p>
|
| 405 |
|
|
<p>rowsel => in6,</p>
|
| 406 |
|
|
<p>res => wren,</p>
|
| 407 |
|
|
<p>x => c(3));</p>
|
| 408 |
|
|
<p>mc35 : mc</p>
|
| 409 |
|
|
<p>PORT MAP (</p>
|
| 410 |
|
|
<p>vss => vss,</p>
|
| 411 |
|
|
<p>vdd => vdd,</p>
|
| 412 |
|
|
<p>y => q5,</p>
|
| 413 |
|
|
<p>wren => res,</p>
|
| 414 |
|
|
<p>rowsel => in5,</p>
|
| 415 |
|
|
<p>res => wren,</p>
|
| 416 |
|
|
<p>x => c(3));</p>
|
| 417 |
|
|
<p>mc34 : mc</p>
|
| 418 |
|
|
<p>PORT MAP (</p>
|
| 419 |
|
|
<p>vss => vss,</p>
|
| 420 |
|
|
<p>vdd => vdd,</p>
|
| 421 |
|
|
<p>y => q4,</p>
|
| 422 |
|
|
<p>wren => res,</p>
|
| 423 |
|
|
<p>rowsel => in4,</p>
|
| 424 |
|
|
<p>res => wren,</p>
|
| 425 |
|
|
<p>x => c(3));</p>
|
| 426 |
|
|
<p>mc33 : mc</p>
|
| 427 |
|
|
<p>PORT MAP (</p>
|
| 428 |
|
|
<p>vss => vss,</p>
|
| 429 |
|
|
<p>vdd => vdd,</p>
|
| 430 |
|
|
<p>y => q3,</p>
|
| 431 |
|
|
<p>wren => res,</p>
|
| 432 |
|
|
<p>rowsel => in3,</p>
|
| 433 |
|
|
<p>res => wren,</p>
|
| 434 |
|
|
<p>x => c(3));</p>
|
| 435 |
|
|
<p>mc32 : mc</p>
|
| 436 |
|
|
<p>PORT MAP (</p>
|
| 437 |
|
|
<p>vss => vss,</p>
|
| 438 |
|
|
<p>vdd => vdd,</p>
|
| 439 |
|
|
<p>y => q2,</p>
|
| 440 |
|
|
<p>wren => res,</p>
|
| 441 |
|
|
<p>rowsel => in2,</p>
|
| 442 |
|
|
<p>res => wren,</p>
|
| 443 |
|
|
<p>x => c(3));</p>
|
| 444 |
|
|
<p>mc31 : mc</p>
|
| 445 |
|
|
<p>PORT MAP (</p>
|
| 446 |
|
|
<p>vss => vss,</p>
|
| 447 |
|
|
<p>vdd => vdd,</p>
|
| 448 |
|
|
<p>y => q1,</p>
|
| 449 |
|
|
<p>wren => res,</p>
|
| 450 |
|
|
<p>rowsel => in1,</p>
|
| 451 |
|
|
<p>res => wren,</p>
|
| 452 |
|
|
<p>x => c(3));</p>
|
| 453 |
|
|
<p>mc30 : mc</p>
|
| 454 |
|
|
<p>PORT MAP (</p>
|
| 455 |
|
|
<p>vss => vss,</p>
|
| 456 |
|
|
<p>vdd => vdd,</p>
|
| 457 |
|
|
<p>y => q0,</p>
|
| 458 |
|
|
<p>wren => res,</p>
|
| 459 |
|
|
<p>rowsel => in0,</p>
|
| 460 |
|
|
<p>res => wren,</p>
|
| 461 |
|
|
<p>x => c(3));</p>
|
| 462 |
|
|
<p>mc47 : mc</p>
|
| 463 |
|
|
<p>PORT MAP (</p>
|
| 464 |
|
|
<p>vss => vss,</p>
|
| 465 |
|
|
<p>vdd => vdd,</p>
|
| 466 |
|
|
<p>y => q7,</p>
|
| 467 |
|
|
<p>wren => res,</p>
|
| 468 |
|
|
<p>rowsel => in7,</p>
|
| 469 |
|
|
<p>res => wren,</p>
|
| 470 |
|
|
<p>x => c(4));</p>
|
| 471 |
|
|
<p>mc46 : mc</p>
|
| 472 |
|
|
<p>PORT MAP (</p>
|
| 473 |
|
|
<p>vss => vss,</p>
|
| 474 |
|
|
<p>vdd => vdd,</p>
|
| 475 |
|
|
<p>y => q6,</p>
|
| 476 |
|
|
<p>wren => res,</p>
|
| 477 |
|
|
<p>rowsel => in6,</p>
|
| 478 |
|
|
<p>res => wren,</p>
|
| 479 |
|
|
<p>x => c(4));</p>
|
| 480 |
|
|
<p>mc45 : mc</p>
|
| 481 |
|
|
<p>PORT MAP (</p>
|
| 482 |
|
|
<p>vss => vss,</p>
|
| 483 |
|
|
<p>vdd => vdd,</p>
|
| 484 |
|
|
<p>y => q5,</p>
|
| 485 |
|
|
<p>wren => res,</p>
|
| 486 |
|
|
<p>rowsel => in5,</p>
|
| 487 |
|
|
<p>res => wren,</p>
|
| 488 |
|
|
<p>x => c(4));</p>
|
| 489 |
|
|
<p>mc44 : mc</p>
|
| 490 |
|
|
<p>PORT MAP (</p>
|
| 491 |
|
|
<p>vss => vss,</p>
|
| 492 |
|
|
<p>vdd => vdd,</p>
|
| 493 |
|
|
<p>y => q4,</p>
|
| 494 |
|
|
<p>wren => res,</p>
|
| 495 |
|
|
<p>rowsel => in4,</p>
|
| 496 |
|
|
<p>res => wren,</p>
|
| 497 |
|
|
<p>x => c(4));</p>
|
| 498 |
|
|
<p>mc43 : mc</p>
|
| 499 |
|
|
<p>PORT MAP (</p>
|
| 500 |
|
|
<p>vss => vss,</p>
|
| 501 |
|
|
<p>vdd => vdd,</p>
|
| 502 |
|
|
<p>y => q3,</p>
|
| 503 |
|
|
<p>wren => res,</p>
|
| 504 |
|
|
<p>rowsel => in3,</p>
|
| 505 |
|
|
<p>res => wren,</p>
|
| 506 |
|
|
<p>x => c(4));</p>
|
| 507 |
|
|
<p>mc42 : mc</p>
|
| 508 |
|
|
<p>PORT MAP (</p>
|
| 509 |
|
|
<p>vss => vss,</p>
|
| 510 |
|
|
<p>vdd => vdd,</p>
|
| 511 |
|
|
<p>y => q2,</p>
|
| 512 |
|
|
<p>wren => res,</p>
|
| 513 |
|
|
<p>rowsel => in2,</p>
|
| 514 |
|
|
<p>res => wren,</p>
|
| 515 |
|
|
<p>x => c(4));</p>
|
| 516 |
|
|
<p>mc41 : mc</p>
|
| 517 |
|
|
<p>PORT MAP (</p>
|
| 518 |
|
|
<p>vss => vss,</p>
|
| 519 |
|
|
<p>vdd => vdd,</p>
|
| 520 |
|
|
<p>y => q1,</p>
|
| 521 |
|
|
<p>wren => res,</p>
|
| 522 |
|
|
<p>rowsel => in1,</p>
|
| 523 |
|
|
<p>res => wren,</p>
|
| 524 |
|
|
<p>x => c(4));</p>
|
| 525 |
|
|
<p>mc40 : mc</p>
|
| 526 |
|
|
<p>PORT MAP (</p>
|
| 527 |
|
|
<p>vss => vss,</p>
|
| 528 |
|
|
<p>vdd => vdd,</p>
|
| 529 |
|
|
<p>y => q0,</p>
|
| 530 |
|
|
<p>wren => res,</p>
|
| 531 |
|
|
<p>rowsel => in0,</p>
|
| 532 |
|
|
<p>res => wren,</p>
|
| 533 |
|
|
<p>x => c(4));</p>
|
| 534 |
|
|
<p>mc57 : mc</p>
|
| 535 |
|
|
<p>PORT MAP (</p>
|
| 536 |
|
|
<p>vss => vss,</p>
|
| 537 |
|
|
<p>vdd => vdd,</p>
|
| 538 |
|
|
<p>y => q7,</p>
|
| 539 |
|
|
<p>wren => res,</p>
|
| 540 |
|
|
<p>rowsel => in7,</p>
|
| 541 |
|
|
<p>res => wren,</p>
|
| 542 |
|
|
<p>x => c(5));</p>
|
| 543 |
|
|
<p>mc56 : mc</p>
|
| 544 |
|
|
<p>PORT MAP (</p>
|
| 545 |
|
|
<p>vss => vss,</p>
|
| 546 |
|
|
<p>vdd => vdd,</p>
|
| 547 |
|
|
<p>y => q6,</p>
|
| 548 |
|
|
<p>wren => res,</p>
|
| 549 |
|
|
<p>rowsel => in6,</p>
|
| 550 |
|
|
<p>res => wren,</p>
|
| 551 |
|
|
<p>x => c(5));</p>
|
| 552 |
|
|
<p>mc55 : mc</p>
|
| 553 |
|
|
<p>PORT MAP (</p>
|
| 554 |
|
|
<p>vss => vss,</p>
|
| 555 |
|
|
<p>vdd => vdd,</p>
|
| 556 |
|
|
<p>y => q5,</p>
|
| 557 |
|
|
<p>wren => res,</p>
|
| 558 |
|
|
<p>rowsel => in5,</p>
|
| 559 |
|
|
<p>res => wren,</p>
|
| 560 |
|
|
<p>x => c(5));</p>
|
| 561 |
|
|
<p>mc54 : mc</p>
|
| 562 |
|
|
<p>PORT MAP (</p>
|
| 563 |
|
|
<p>vss => vss,</p>
|
| 564 |
|
|
<p>vdd => vdd,</p>
|
| 565 |
|
|
<p>y => q4,</p>
|
| 566 |
|
|
<p>wren => res,</p>
|
| 567 |
|
|
<p>rowsel => in4,</p>
|
| 568 |
|
|
<p>res => wren,</p>
|
| 569 |
|
|
<p>x => c(5));</p>
|
| 570 |
|
|
<p>mc53 : mc</p>
|
| 571 |
|
|
<p>PORT MAP (</p>
|
| 572 |
|
|
<p>vss => vss,</p>
|
| 573 |
|
|
<p>vdd => vdd,</p>
|
| 574 |
|
|
<p>y => q3,</p>
|
| 575 |
|
|
<p>wren => res,</p>
|
| 576 |
|
|
<p>rowsel => in3,</p>
|
| 577 |
|
|
<p>res => wren,</p>
|
| 578 |
|
|
<p>x => c(5));</p>
|
| 579 |
|
|
<p>mc52 : mc</p>
|
| 580 |
|
|
<p>PORT MAP (</p>
|
| 581 |
|
|
<p>vss => vss,</p>
|
| 582 |
|
|
<p>vdd => vdd,</p>
|
| 583 |
|
|
<p>y => q2,</p>
|
| 584 |
|
|
<p>wren => res,</p>
|
| 585 |
|
|
<p>rowsel => in2,</p>
|
| 586 |
|
|
<p>res => wren,</p>
|
| 587 |
|
|
<p>x => c(5));</p>
|
| 588 |
|
|
<p>mc51 : mc</p>
|
| 589 |
|
|
<p>PORT MAP (</p>
|
| 590 |
|
|
<p>vss => vss,</p>
|
| 591 |
|
|
<p>vdd => vdd,</p>
|
| 592 |
|
|
<p>y => q1,</p>
|
| 593 |
|
|
<p>wren => res,</p>
|
| 594 |
|
|
<p>rowsel => in1,</p>
|
| 595 |
|
|
<p>res => wren,</p>
|
| 596 |
|
|
<p>x => c(5));</p>
|
| 597 |
|
|
<p>mc50 : mc</p>
|
| 598 |
|
|
<p>PORT MAP (</p>
|
| 599 |
|
|
<p>vss => vss,</p>
|
| 600 |
|
|
<p>vdd => vdd,</p>
|
| 601 |
|
|
<p>y => q0,</p>
|
| 602 |
|
|
<p>wren => res,</p>
|
| 603 |
|
|
<p>rowsel => in0,</p>
|
| 604 |
|
|
<p>res => wren,</p>
|
| 605 |
|
|
<p>x => c(5));</p>
|
| 606 |
|
|
<p>mc67 : mc</p>
|
| 607 |
|
|
<p>PORT MAP (</p>
|
| 608 |
|
|
<p>vss => vss,</p>
|
| 609 |
|
|
<p>vdd => vdd,</p>
|
| 610 |
|
|
<p>y => q7,</p>
|
| 611 |
|
|
<p>wren => res,</p>
|
| 612 |
|
|
<p>rowsel => in7,</p>
|
| 613 |
|
|
<p>res => wren,</p>
|
| 614 |
|
|
<p>x => c(6));</p>
|
| 615 |
|
|
<p>mc66 : mc</p>
|
| 616 |
|
|
<p>PORT MAP (</p>
|
| 617 |
|
|
<p>vss => vss,</p>
|
| 618 |
|
|
<p>vdd => vdd,</p>
|
| 619 |
|
|
<p>y => q6,</p>
|
| 620 |
|
|
<p>wren => res,</p>
|
| 621 |
|
|
<p>rowsel => in6,</p>
|
| 622 |
|
|
<p>res => wren,</p>
|
| 623 |
|
|
<p>x => c(6));</p>
|
| 624 |
|
|
<p>mc65 : mc</p>
|
| 625 |
|
|
<p>PORT MAP (</p>
|
| 626 |
|
|
<p>vss => vss,</p>
|
| 627 |
|
|
<p>vdd => vdd,</p>
|
| 628 |
|
|
<p>y => q5,</p>
|
| 629 |
|
|
<p>wren => res,</p>
|
| 630 |
|
|
<p>rowsel => in5,</p>
|
| 631 |
|
|
<p>res => wren,</p>
|
| 632 |
|
|
<p>x => c(6));</p>
|
| 633 |
|
|
<p>mc64 : mc</p>
|
| 634 |
|
|
<p>PORT MAP (</p>
|
| 635 |
|
|
<p>vss => vss,</p>
|
| 636 |
|
|
<p>vdd => vdd,</p>
|
| 637 |
|
|
<p>y => q4,</p>
|
| 638 |
|
|
<p>wren => res,</p>
|
| 639 |
|
|
<p>rowsel => in4,</p>
|
| 640 |
|
|
<p>res => wren,</p>
|
| 641 |
|
|
<p>x => c(6));</p>
|
| 642 |
|
|
<p>mc63 : mc</p>
|
| 643 |
|
|
<p>PORT MAP (</p>
|
| 644 |
|
|
<p>vss => vss,</p>
|
| 645 |
|
|
<p>vdd => vdd,</p>
|
| 646 |
|
|
<p>y => q3,</p>
|
| 647 |
|
|
<p>wren => res,</p>
|
| 648 |
|
|
<p>rowsel => in3,</p>
|
| 649 |
|
|
<p>res => wren,</p>
|
| 650 |
|
|
<p>x => c(6));</p>
|
| 651 |
|
|
<p>mc62 : mc</p>
|
| 652 |
|
|
<p>PORT MAP (</p>
|
| 653 |
|
|
<p>vss => vss,</p>
|
| 654 |
|
|
<p>vdd => vdd,</p>
|
| 655 |
|
|
<p>y => q2,</p>
|
| 656 |
|
|
<p>wren => res,</p>
|
| 657 |
|
|
<p>rowsel => in2,</p>
|
| 658 |
|
|
<p>res => wren,</p>
|
| 659 |
|
|
<p>x => c(6));</p>
|
| 660 |
|
|
<p>mc61 : mc</p>
|
| 661 |
|
|
<p>PORT MAP (</p>
|
| 662 |
|
|
<p>vss => vss,</p>
|
| 663 |
|
|
<p>vdd => vdd,</p>
|
| 664 |
|
|
<p>y => q1,</p>
|
| 665 |
|
|
<p>wren => res,</p>
|
| 666 |
|
|
<p>rowsel => in1,</p>
|
| 667 |
|
|
<p>res => wren,</p>
|
| 668 |
|
|
<p>x => c(6));</p>
|
| 669 |
|
|
<p>mc60 : mc</p>
|
| 670 |
|
|
<p>PORT MAP (</p>
|
| 671 |
|
|
<p>vss => vss,</p>
|
| 672 |
|
|
<p>vdd => vdd,</p>
|
| 673 |
|
|
<p>y => q0,</p>
|
| 674 |
|
|
<p>wren => res,</p>
|
| 675 |
|
|
<p>rowsel => in0,</p>
|
| 676 |
|
|
<p>res => wren,</p>
|
| 677 |
|
|
<p>x => c(6));</p>
|
| 678 |
|
|
<p>mc77 : mc</p>
|
| 679 |
|
|
<p>PORT MAP (</p>
|
| 680 |
|
|
<p>vss => vss,</p>
|
| 681 |
|
|
<p>vdd => vdd,</p>
|
| 682 |
|
|
<p>y => q7,</p>
|
| 683 |
|
|
<p>wren => res,</p>
|
| 684 |
|
|
<p>rowsel => in7,</p>
|
| 685 |
|
|
<p>res => wren,</p>
|
| 686 |
|
|
<p>x => c(7));</p>
|
| 687 |
|
|
<p>mc76 : mc</p>
|
| 688 |
|
|
<p>PORT MAP (</p>
|
| 689 |
|
|
<p>vss => vss,</p>
|
| 690 |
|
|
<p>vdd => vdd,</p>
|
| 691 |
|
|
<p>y => q6,</p>
|
| 692 |
|
|
<p>wren => res,</p>
|
| 693 |
|
|
<p>rowsel => in6,</p>
|
| 694 |
|
|
<p>res => wren,</p>
|
| 695 |
|
|
<p>x => c(7));</p>
|
| 696 |
|
|
<p>mc75 : mc</p>
|
| 697 |
|
|
<p>PORT MAP (</p>
|
| 698 |
|
|
<p>vss => vss,</p>
|
| 699 |
|
|
<p>vdd => vdd,</p>
|
| 700 |
|
|
<p>y => q5,</p>
|
| 701 |
|
|
<p>wren => res,</p>
|
| 702 |
|
|
<p>rowsel => in5,</p>
|
| 703 |
|
|
<p>res => wren,</p>
|
| 704 |
|
|
<p>x => c(7));</p>
|
| 705 |
|
|
<p>mc74 : mc</p>
|
| 706 |
|
|
<p>PORT MAP (</p>
|
| 707 |
|
|
<p>vss => vss,</p>
|
| 708 |
|
|
<p>vdd => vdd,</p>
|
| 709 |
|
|
<p>y => q4,</p>
|
| 710 |
|
|
<p>wren => res,</p>
|
| 711 |
|
|
<p>rowsel => in4,</p>
|
| 712 |
|
|
<p>res => wren,</p>
|
| 713 |
|
|
<p>x => c(7));</p>
|
| 714 |
|
|
<p>mc73 : mc</p>
|
| 715 |
|
|
<p>PORT MAP (</p>
|
| 716 |
|
|
<p>vss => vss,</p>
|
| 717 |
|
|
<p>vdd => vdd,</p>
|
| 718 |
|
|
<p>y => q3,</p>
|
| 719 |
|
|
<p>wren => res,</p>
|
| 720 |
|
|
<p>rowsel => in3,</p>
|
| 721 |
|
|
<p>res => wren,</p>
|
| 722 |
|
|
<p>x => c(7));</p>
|
| 723 |
|
|
<p>mc72 : mc</p>
|
| 724 |
|
|
<p>PORT MAP (</p>
|
| 725 |
|
|
<p>vss => vss,</p>
|
| 726 |
|
|
<p>vdd => vdd,</p>
|
| 727 |
|
|
<p>y => q2,</p>
|
| 728 |
|
|
<p>wren => res,</p>
|
| 729 |
|
|
<p>rowsel => in2,</p>
|
| 730 |
|
|
<p>res => wren,</p>
|
| 731 |
|
|
<p>x => c(7));</p>
|
| 732 |
|
|
<p>mc71 : mc</p>
|
| 733 |
|
|
<p>PORT MAP (</p>
|
| 734 |
|
|
<p>vss => vss,</p>
|
| 735 |
|
|
<p>vdd => vdd,</p>
|
| 736 |
|
|
<p>y => q1,</p>
|
| 737 |
|
|
<p>wren => res,</p>
|
| 738 |
|
|
<p>rowsel => in1,</p>
|
| 739 |
|
|
<p>res => wren,</p>
|
| 740 |
|
|
<p>x => c(7));</p>
|
| 741 |
|
|
<p>mc70 : mc</p>
|
| 742 |
|
|
<p>PORT MAP (</p>
|
| 743 |
|
|
<p>vss => vss,</p>
|
| 744 |
|
|
<p>vdd => vdd,</p>
|
| 745 |
|
|
<p>y => q0,</p>
|
| 746 |
|
|
<p>wren => res,</p>
|
| 747 |
|
|
<p>rowsel => in0,</p>
|
| 748 |
|
|
<p>res => wren,</p>
|
| 749 |
|
|
<p>x => c(7));</p>
|
| 750 |
|
|
<p>mc87 : mc</p>
|
| 751 |
|
|
<p>PORT MAP (</p>
|
| 752 |
|
|
<p>vss => vss,</p>
|
| 753 |
|
|
<p>vdd => vdd,</p>
|
| 754 |
|
|
<p>y => q7,</p>
|
| 755 |
|
|
<p>wren => res,</p>
|
| 756 |
|
|
<p>rowsel => in7,</p>
|
| 757 |
|
|
<p>res => wren,</p>
|
| 758 |
|
|
<p>x => c(8));</p>
|
| 759 |
|
|
<p>mc86 : mc</p>
|
| 760 |
|
|
<p>PORT MAP (</p>
|
| 761 |
|
|
<p>vss => vss,</p>
|
| 762 |
|
|
<p>vdd => vdd,</p>
|
| 763 |
|
|
<p>y => q6,</p>
|
| 764 |
|
|
<p>wren => res,</p>
|
| 765 |
|
|
<p>rowsel => in6,</p>
|
| 766 |
|
|
<p>res => wren,</p>
|
| 767 |
|
|
<p>x => c(8));</p>
|
| 768 |
|
|
<p>mc85 : mc</p>
|
| 769 |
|
|
<p>PORT MAP (</p>
|
| 770 |
|
|
<p>vss => vss,</p>
|
| 771 |
|
|
<p>vdd => vdd,</p>
|
| 772 |
|
|
<p>y => q5,</p>
|
| 773 |
|
|
<p>wren => res,</p>
|
| 774 |
|
|
<p>rowsel => in5,</p>
|
| 775 |
|
|
<p>res => wren,</p>
|
| 776 |
|
|
<p>x => c(8));</p>
|
| 777 |
|
|
<p>mc84 : mc</p>
|
| 778 |
|
|
<p>PORT MAP (</p>
|
| 779 |
|
|
<p>vss => vss,</p>
|
| 780 |
|
|
<p>vdd => vdd,</p>
|
| 781 |
|
|
<p>y => q4,</p>
|
| 782 |
|
|
<p>wren => res,</p>
|
| 783 |
|
|
<p>rowsel => in4,</p>
|
| 784 |
|
|
<p>res => wren,</p>
|
| 785 |
|
|
<p>x => c(8));</p>
|
| 786 |
|
|
<p>mc83 : mc</p>
|
| 787 |
|
|
<p>PORT MAP (</p>
|
| 788 |
|
|
<p>vss => vss,</p>
|
| 789 |
|
|
<p>vdd => vdd,</p>
|
| 790 |
|
|
<p>y => q3,</p>
|
| 791 |
|
|
<p>wren => res,</p>
|
| 792 |
|
|
<p>rowsel => in3,</p>
|
| 793 |
|
|
<p>res => wren,</p>
|
| 794 |
|
|
<p>x => c(8));</p>
|
| 795 |
|
|
<p>mc82 : mc</p>
|
| 796 |
|
|
<p>PORT MAP (</p>
|
| 797 |
|
|
<p>vss => vss,</p>
|
| 798 |
|
|
<p>vdd => vdd,</p>
|
| 799 |
|
|
<p>y => q2,</p>
|
| 800 |
|
|
<p>wren => res,</p>
|
| 801 |
|
|
<p>rowsel => in2,</p>
|
| 802 |
|
|
<p>res => wren,</p>
|
| 803 |
|
|
<p>x => c(8));</p>
|
| 804 |
|
|
<p>mc81 : mc</p>
|
| 805 |
|
|
<p>PORT MAP (</p>
|
| 806 |
|
|
<p>vss => vss,</p>
|
| 807 |
|
|
<p>vdd => vdd,</p>
|
| 808 |
|
|
<p>y => q1,</p>
|
| 809 |
|
|
<p>wren => res,</p>
|
| 810 |
|
|
<p>rowsel => in1,</p>
|
| 811 |
|
|
<p>res => wren,</p>
|
| 812 |
|
|
<p>x => c(8));</p>
|
| 813 |
|
|
<p>mc80 : mc</p>
|
| 814 |
|
|
<p>PORT MAP (</p>
|
| 815 |
|
|
<p>vss => vss,</p>
|
| 816 |
|
|
<p>vdd => vdd,</p>
|
| 817 |
|
|
<p>y => q0,</p>
|
| 818 |
|
|
<p>wren => res,</p>
|
| 819 |
|
|
<p>rowsel => in0,</p>
|
| 820 |
|
|
<p>res => wren,</p>
|
| 821 |
|
|
<p>x => c(8));</p>
|
| 822 |
|
|
<p>mc97 : mc</p>
|
| 823 |
|
|
<p>PORT MAP (</p>
|
| 824 |
|
|
<p>vss => vss,</p>
|
| 825 |
|
|
<p>vdd => vdd,</p>
|
| 826 |
|
|
<p>y => q7,</p>
|
| 827 |
|
|
<p>wren => res,</p>
|
| 828 |
|
|
<p>rowsel => in7,</p>
|
| 829 |
|
|
<p>res => wren,</p>
|
| 830 |
|
|
<p>x => c(9));</p>
|
| 831 |
|
|
<p>mc96 : mc</p>
|
| 832 |
|
|
<p>PORT MAP (</p>
|
| 833 |
|
|
<p>vss => vss,</p>
|
| 834 |
|
|
<p>vdd => vdd,</p>
|
| 835 |
|
|
<p>y => q6,</p>
|
| 836 |
|
|
<p>wren => res,</p>
|
| 837 |
|
|
<p>rowsel => in6,</p>
|
| 838 |
|
|
<p>res => wren,</p>
|
| 839 |
|
|
<p>x => c(9));</p>
|
| 840 |
|
|
<p>mc95 : mc</p>
|
| 841 |
|
|
<p>PORT MAP (</p>
|
| 842 |
|
|
<p>vss => vss,</p>
|
| 843 |
|
|
<p>vdd => vdd,</p>
|
| 844 |
|
|
<p>y => q5,</p>
|
| 845 |
|
|
<p>wren => res,</p>
|
| 846 |
|
|
<p>rowsel => in5,</p>
|
| 847 |
|
|
<p>res => wren,</p>
|
| 848 |
|
|
<p>x => c(9));</p>
|
| 849 |
|
|
<p>mc94 : mc</p>
|
| 850 |
|
|
<p>PORT MAP (</p>
|
| 851 |
|
|
<p>vss => vss,</p>
|
| 852 |
|
|
<p>vdd => vdd,</p>
|
| 853 |
|
|
<p>y => q4,</p>
|
| 854 |
|
|
<p>wren => res,</p>
|
| 855 |
|
|
<p>rowsel => in4,</p>
|
| 856 |
|
|
<p>res => wren,</p>
|
| 857 |
|
|
<p>x => c(9));</p>
|
| 858 |
|
|
<p>mc93 : mc</p>
|
| 859 |
|
|
<p>PORT MAP (</p>
|
| 860 |
|
|
<p>vss => vss,</p>
|
| 861 |
|
|
<p>vdd => vdd,</p>
|
| 862 |
|
|
<p>y => q3,</p>
|
| 863 |
|
|
<p>wren => res,</p>
|
| 864 |
|
|
<p>rowsel => in3,</p>
|
| 865 |
|
|
<p>res => wren,</p>
|
| 866 |
|
|
<p>x => c(9));</p>
|
| 867 |
|
|
<p>mc92 : mc</p>
|
| 868 |
|
|
<p>PORT MAP (</p>
|
| 869 |
|
|
<p>vss => vss,</p>
|
| 870 |
|
|
<p>vdd => vdd,</p>
|
| 871 |
|
|
<p>y => q2,</p>
|
| 872 |
|
|
<p>wren => res,</p>
|
| 873 |
|
|
<p>rowsel => in2,</p>
|
| 874 |
|
|
<p>res => wren,</p>
|
| 875 |
|
|
<p>x => c(9));</p>
|
| 876 |
|
|
<p>mc91 : mc</p>
|
| 877 |
|
|
<p>PORT MAP (</p>
|
| 878 |
|
|
<p>vss => vss,</p>
|
| 879 |
|
|
<p>vdd => vdd,</p>
|
| 880 |
|
|
<p>y => q1,</p>
|
| 881 |
|
|
<p>wren => res,</p>
|
| 882 |
|
|
<p>rowsel => in1,</p>
|
| 883 |
|
|
<p>res => wren,</p>
|
| 884 |
|
|
<p>x => c(9));</p>
|
| 885 |
|
|
<p>mc90 : mc</p>
|
| 886 |
|
|
<p>PORT MAP (</p>
|
| 887 |
|
|
<p>vss => vss,</p>
|
| 888 |
|
|
<p>vdd => vdd,</p>
|
| 889 |
|
|
<p>y => q0,</p>
|
| 890 |
|
|
<p>wren => res,</p>
|
| 891 |
|
|
<p>rowsel => in0,</p>
|
| 892 |
|
|
<p>res => wren,</p>
|
| 893 |
|
|
<p>x => c(9));</p>
|
| 894 |
|
|
<p>mc107 : mc</p>
|
| 895 |
|
|
<p>PORT MAP (</p>
|
| 896 |
|
|
<p>vss => vss,</p>
|
| 897 |
|
|
<p>vdd => vdd,</p>
|
| 898 |
|
|
<p>y => q7,</p>
|
| 899 |
|
|
<p>wren => res,</p>
|
| 900 |
|
|
<p>rowsel => in7,</p>
|
| 901 |
|
|
<p>res => wren,</p>
|
| 902 |
|
|
<p>x => c(10));</p>
|
| 903 |
|
|
<p>mc106 : mc</p>
|
| 904 |
|
|
<p>PORT MAP (</p>
|
| 905 |
|
|
<p>vss => vss,</p>
|
| 906 |
|
|
<p>vdd => vdd,</p>
|
| 907 |
|
|
<p>y => q6,</p>
|
| 908 |
|
|
<p>wren => res,</p>
|
| 909 |
|
|
<p>rowsel => in6,</p>
|
| 910 |
|
|
<p>res => wren,</p>
|
| 911 |
|
|
<p>x => c(10));</p>
|
| 912 |
|
|
<p>mc105 : mc</p>
|
| 913 |
|
|
<p>PORT MAP (</p>
|
| 914 |
|
|
<p>vss => vss,</p>
|
| 915 |
|
|
<p>vdd => vdd,</p>
|
| 916 |
|
|
<p>y => q5,</p>
|
| 917 |
|
|
<p>wren => res,</p>
|
| 918 |
|
|
<p>rowsel => in5,</p>
|
| 919 |
|
|
<p>res => wren,</p>
|
| 920 |
|
|
<p>x => c(10));</p>
|
| 921 |
|
|
<p>mc104 : mc</p>
|
| 922 |
|
|
<p>PORT MAP (</p>
|
| 923 |
|
|
<p>vss => vss,</p>
|
| 924 |
|
|
<p>vdd => vdd,</p>
|
| 925 |
|
|
<p>y => q4,</p>
|
| 926 |
|
|
<p>wren => res,</p>
|
| 927 |
|
|
<p>rowsel => in4,</p>
|
| 928 |
|
|
<p>res => wren,</p>
|
| 929 |
|
|
<p>x => c(10));</p>
|
| 930 |
|
|
<p>mc103 : mc</p>
|
| 931 |
|
|
<p>PORT MAP (</p>
|
| 932 |
|
|
<p>vss => vss,</p>
|
| 933 |
|
|
<p>vdd => vdd,</p>
|
| 934 |
|
|
<p>y => q3,</p>
|
| 935 |
|
|
<p>wren => res,</p>
|
| 936 |
|
|
<p>rowsel => in3,</p>
|
| 937 |
|
|
<p>res => wren,</p>
|
| 938 |
|
|
<p>x => c(10));</p>
|
| 939 |
|
|
<p>mc102 : mc</p>
|
| 940 |
|
|
<p>PORT MAP (</p>
|
| 941 |
|
|
<p>vss => vss,</p>
|
| 942 |
|
|
<p>vdd => vdd,</p>
|
| 943 |
|
|
<p>y => q2,</p>
|
| 944 |
|
|
<p>wren => res,</p>
|
| 945 |
|
|
<p>rowsel => in2,</p>
|
| 946 |
|
|
<p>res => wren,</p>
|
| 947 |
|
|
<p>x => c(10));</p>
|
| 948 |
|
|
<p>mc101 : mc</p>
|
| 949 |
|
|
<p>PORT MAP (</p>
|
| 950 |
|
|
<p>vss => vss,</p>
|
| 951 |
|
|
<p>vdd => vdd,</p>
|
| 952 |
|
|
<p>y => q1,</p>
|
| 953 |
|
|
<p>wren => res,</p>
|
| 954 |
|
|
<p>rowsel => in1,</p>
|
| 955 |
|
|
<p>res => wren,</p>
|
| 956 |
|
|
<p>x => c(10));</p>
|
| 957 |
|
|
<p>mc100 : mc</p>
|
| 958 |
|
|
<p>PORT MAP (</p>
|
| 959 |
|
|
<p>vss => vss,</p>
|
| 960 |
|
|
<p>vdd => vdd,</p>
|
| 961 |
|
|
<p>y => q0,</p>
|
| 962 |
|
|
<p>wren => res,</p>
|
| 963 |
|
|
<p>rowsel => in0,</p>
|
| 964 |
|
|
<p>res => wren,</p>
|
| 965 |
|
|
<p>x => c(10));</p>
|
| 966 |
|
|
<p>mc117 : mc</p>
|
| 967 |
|
|
<p>PORT MAP (</p>
|
| 968 |
|
|
<p>vss => vss,</p>
|
| 969 |
|
|
<p>vdd => vdd,</p>
|
| 970 |
|
|
<p>y => q7,</p>
|
| 971 |
|
|
<p>wren => res,</p>
|
| 972 |
|
|
<p>rowsel => in7,</p>
|
| 973 |
|
|
<p>res => wren,</p>
|
| 974 |
|
|
<p>x => c(11));</p>
|
| 975 |
|
|
<p>mc116 : mc</p>
|
| 976 |
|
|
<p>PORT MAP (</p>
|
| 977 |
|
|
<p>vss => vss,</p>
|
| 978 |
|
|
<p>vdd => vdd,</p>
|
| 979 |
|
|
<p>y => q6,</p>
|
| 980 |
|
|
<p>wren => res,</p>
|
| 981 |
|
|
<p>rowsel => in6,</p>
|
| 982 |
|
|
<p>res => wren,</p>
|
| 983 |
|
|
<p>x => c(11));</p>
|
| 984 |
|
|
<p>mc115 : mc</p>
|
| 985 |
|
|
<p>PORT MAP (</p>
|
| 986 |
|
|
<p>vss => vss,</p>
|
| 987 |
|
|
<p>vdd => vdd,</p>
|
| 988 |
|
|
<p>y => q5,</p>
|
| 989 |
|
|
<p>wren => res,</p>
|
| 990 |
|
|
<p>rowsel => in5,</p>
|
| 991 |
|
|
<p>res => wren,</p>
|
| 992 |
|
|
<p>x => c(11));</p>
|
| 993 |
|
|
<p>mc114 : mc</p>
|
| 994 |
|
|
<p>PORT MAP (</p>
|
| 995 |
|
|
<p>vss => vss,</p>
|
| 996 |
|
|
<p>vdd => vdd,</p>
|
| 997 |
|
|
<p>y => q4,</p>
|
| 998 |
|
|
<p>wren => res,</p>
|
| 999 |
|
|
<p>rowsel => in4,</p>
|
| 1000 |
|
|
<p>res => wren,</p>
|
| 1001 |
|
|
<p>x => c(11));</p>
|
| 1002 |
|
|
<p>mc113 : mc</p>
|
| 1003 |
|
|
<p>PORT MAP (</p>
|
| 1004 |
|
|
<p>vss => vss,</p>
|
| 1005 |
|
|
<p>vdd => vdd,</p>
|
| 1006 |
|
|
<p>y => q3,</p>
|
| 1007 |
|
|
<p>wren => res,</p>
|
| 1008 |
|
|
<p>rowsel => in3,</p>
|
| 1009 |
|
|
<p>res => wren,</p>
|
| 1010 |
|
|
<p>x => c(11));</p>
|
| 1011 |
|
|
<p>mc112 : mc</p>
|
| 1012 |
|
|
<p>PORT MAP (</p>
|
| 1013 |
|
|
<p>vss => vss,</p>
|
| 1014 |
|
|
<p>vdd => vdd,</p>
|
| 1015 |
|
|
<p>y => q2,</p>
|
| 1016 |
|
|
<p>wren => res,</p>
|
| 1017 |
|
|
<p>rowsel => in2,</p>
|
| 1018 |
|
|
<p>res => wren,</p>
|
| 1019 |
|
|
<p>x => c(11));</p>
|
| 1020 |
|
|
<p>mc111 : mc</p>
|
| 1021 |
|
|
<p>PORT MAP (</p>
|
| 1022 |
|
|
<p>vss => vss,</p>
|
| 1023 |
|
|
<p>vdd => vdd,</p>
|
| 1024 |
|
|
<p>y => q1,</p>
|
| 1025 |
|
|
<p>wren => res,</p>
|
| 1026 |
|
|
<p>rowsel => in1,</p>
|
| 1027 |
|
|
<p>res => wren,</p>
|
| 1028 |
|
|
<p>x => c(11));</p>
|
| 1029 |
|
|
<p>mc110 : mc</p>
|
| 1030 |
|
|
<p>PORT MAP (</p>
|
| 1031 |
|
|
<p>vss => vss,</p>
|
| 1032 |
|
|
<p>vdd => vdd,</p>
|
| 1033 |
|
|
<p>y => q0,</p>
|
| 1034 |
|
|
<p>wren => res,</p>
|
| 1035 |
|
|
<p>rowsel => in0,</p>
|
| 1036 |
|
|
<p>res => wren,</p>
|
| 1037 |
|
|
<p>x => c(11));</p>
|
| 1038 |
|
|
<p>mc127 : mc</p>
|
| 1039 |
|
|
<p>PORT MAP (</p>
|
| 1040 |
|
|
<p>vss => vss,</p>
|
| 1041 |
|
|
<p>vdd => vdd,</p>
|
| 1042 |
|
|
<p>y => q7,</p>
|
| 1043 |
|
|
<p>wren => res,</p>
|
| 1044 |
|
|
<p>rowsel => in7,</p>
|
| 1045 |
|
|
<p>res => wren,</p>
|
| 1046 |
|
|
<p>x => c(12));</p>
|
| 1047 |
|
|
<p>mc126 : mc</p>
|
| 1048 |
|
|
<p>PORT MAP (</p>
|
| 1049 |
|
|
<p>vss => vss,</p>
|
| 1050 |
|
|
<p>vdd => vdd,</p>
|
| 1051 |
|
|
<p>y => q6,</p>
|
| 1052 |
|
|
<p>wren => res,</p>
|
| 1053 |
|
|
<p>rowsel => in6,</p>
|
| 1054 |
|
|
<p>res => wren,</p>
|
| 1055 |
|
|
<p>x => c(12));</p>
|
| 1056 |
|
|
<p>mc125 : mc</p>
|
| 1057 |
|
|
<p>PORT MAP (</p>
|
| 1058 |
|
|
<p>vss => vss,</p>
|
| 1059 |
|
|
<p>vdd => vdd,</p>
|
| 1060 |
|
|
<p>y => q5,</p>
|
| 1061 |
|
|
<p>wren => res,</p>
|
| 1062 |
|
|
<p>rowsel => in5,</p>
|
| 1063 |
|
|
<p>res => wren,</p>
|
| 1064 |
|
|
<p>x => c(12));</p>
|
| 1065 |
|
|
<p>mc124 : mc</p>
|
| 1066 |
|
|
<p>PORT MAP (</p>
|
| 1067 |
|
|
<p>vss => vss,</p>
|
| 1068 |
|
|
<p>vdd => vdd,</p>
|
| 1069 |
|
|
<p>y => q4,</p>
|
| 1070 |
|
|
<p>wren => res,</p>
|
| 1071 |
|
|
<p>rowsel => in4,</p>
|
| 1072 |
|
|
<p>res => wren,</p>
|
| 1073 |
|
|
<p>x => c(12));</p>
|
| 1074 |
|
|
<p>mc123 : mc</p>
|
| 1075 |
|
|
<p>PORT MAP (</p>
|
| 1076 |
|
|
<p>vss => vss,</p>
|
| 1077 |
|
|
<p>vdd => vdd,</p>
|
| 1078 |
|
|
<p>y => q3,</p>
|
| 1079 |
|
|
<p>wren => res,</p>
|
| 1080 |
|
|
<p>rowsel => in3,</p>
|
| 1081 |
|
|
<p>res => wren,</p>
|
| 1082 |
|
|
<p>x => c(12));</p>
|
| 1083 |
|
|
<p>mc122 : mc</p>
|
| 1084 |
|
|
<p>PORT MAP (</p>
|
| 1085 |
|
|
<p>vss => vss,</p>
|
| 1086 |
|
|
<p>vdd => vdd,</p>
|
| 1087 |
|
|
<p>y => q2,</p>
|
| 1088 |
|
|
<p>wren => res,</p>
|
| 1089 |
|
|
<p>rowsel => in2,</p>
|
| 1090 |
|
|
<p>res => wren,</p>
|
| 1091 |
|
|
<p>x => c(12));</p>
|
| 1092 |
|
|
<p>mc121 : mc</p>
|
| 1093 |
|
|
<p>PORT MAP (</p>
|
| 1094 |
|
|
<p>vss => vss,</p>
|
| 1095 |
|
|
<p>vdd => vdd,</p>
|
| 1096 |
|
|
<p>y => q1,</p>
|
| 1097 |
|
|
<p>wren => res,</p>
|
| 1098 |
|
|
<p>rowsel => in1,</p>
|
| 1099 |
|
|
<p>res => wren,</p>
|
| 1100 |
|
|
<p>x => c(12));</p>
|
| 1101 |
|
|
<p>mc120 : mc</p>
|
| 1102 |
|
|
<p>PORT MAP (</p>
|
| 1103 |
|
|
<p>vss => vss,</p>
|
| 1104 |
|
|
<p>vdd => vdd,</p>
|
| 1105 |
|
|
<p>y => q0,</p>
|
| 1106 |
|
|
<p>wren => res,</p>
|
| 1107 |
|
|
<p>rowsel => in0,</p>
|
| 1108 |
|
|
<p>res => wren,</p>
|
| 1109 |
|
|
<p>x => c(12));</p>
|
| 1110 |
|
|
<p>mc137 : mc</p>
|
| 1111 |
|
|
<p>PORT MAP (</p>
|
| 1112 |
|
|
<p>vss => vss,</p>
|
| 1113 |
|
|
<p>vdd => vdd,</p>
|
| 1114 |
|
|
<p>y => q7,</p>
|
| 1115 |
|
|
<p>wren => res,</p>
|
| 1116 |
|
|
<p>rowsel => in7,</p>
|
| 1117 |
|
|
<p>res => wren,</p>
|
| 1118 |
|
|
<p>x => c(13));</p>
|
| 1119 |
|
|
<p>mc136 : mc</p>
|
| 1120 |
|
|
<p>PORT MAP (</p>
|
| 1121 |
|
|
<p>vss => vss,</p>
|
| 1122 |
|
|
<p>vdd => vdd,</p>
|
| 1123 |
|
|
<p>y => q6,</p>
|
| 1124 |
|
|
<p>wren => res,</p>
|
| 1125 |
|
|
<p>rowsel => in6,</p>
|
| 1126 |
|
|
<p>res => wren,</p>
|
| 1127 |
|
|
<p>x => c(13));</p>
|
| 1128 |
|
|
<p>mc135 : mc</p>
|
| 1129 |
|
|
<p>PORT MAP (</p>
|
| 1130 |
|
|
<p>vss => vss,</p>
|
| 1131 |
|
|
<p>vdd => vdd,</p>
|
| 1132 |
|
|
<p>y => q5,</p>
|
| 1133 |
|
|
<p>wren => res,</p>
|
| 1134 |
|
|
<p>rowsel => in5,</p>
|
| 1135 |
|
|
<p>res => wren,</p>
|
| 1136 |
|
|
<p>x => c(13));</p>
|
| 1137 |
|
|
<p>mc134 : mc</p>
|
| 1138 |
|
|
<p>PORT MAP (</p>
|
| 1139 |
|
|
<p>vss => vss,</p>
|
| 1140 |
|
|
<p>vdd => vdd,</p>
|
| 1141 |
|
|
<p>y => q4,</p>
|
| 1142 |
|
|
<p>wren => res,</p>
|
| 1143 |
|
|
<p>rowsel => in4,</p>
|
| 1144 |
|
|
<p>res => wren,</p>
|
| 1145 |
|
|
<p>x => c(13));</p>
|
| 1146 |
|
|
<p>mc133 : mc</p>
|
| 1147 |
|
|
<p>PORT MAP (</p>
|
| 1148 |
|
|
<p>vss => vss,</p>
|
| 1149 |
|
|
<p>vdd => vdd,</p>
|
| 1150 |
|
|
<p>y => q3,</p>
|
| 1151 |
|
|
<p>wren => res,</p>
|
| 1152 |
|
|
<p>rowsel => in3,</p>
|
| 1153 |
|
|
<p>res => wren,</p>
|
| 1154 |
|
|
<p>x => c(13));</p>
|
| 1155 |
|
|
<p>mc132 : mc</p>
|
| 1156 |
|
|
<p>PORT MAP (</p>
|
| 1157 |
|
|
<p>vss => vss,</p>
|
| 1158 |
|
|
<p>vdd => vdd,</p>
|
| 1159 |
|
|
<p>y => q2,</p>
|
| 1160 |
|
|
<p>wren => res,</p>
|
| 1161 |
|
|
<p>rowsel => in2,</p>
|
| 1162 |
|
|
<p>res => wren,</p>
|
| 1163 |
|
|
<p>x => c(13));</p>
|
| 1164 |
|
|
<p>mc131 : mc</p>
|
| 1165 |
|
|
<p>PORT MAP (</p>
|
| 1166 |
|
|
<p>vss => vss,</p>
|
| 1167 |
|
|
<p>vdd => vdd,</p>
|
| 1168 |
|
|
<p>y => q1,</p>
|
| 1169 |
|
|
<p>wren => res,</p>
|
| 1170 |
|
|
<p>rowsel => in1,</p>
|
| 1171 |
|
|
<p>res => wren,</p>
|
| 1172 |
|
|
<p>x => c(13));</p>
|
| 1173 |
|
|
<p>mc130 : mc</p>
|
| 1174 |
|
|
<p>PORT MAP (</p>
|
| 1175 |
|
|
<p>vss => vss,</p>
|
| 1176 |
|
|
<p>vdd => vdd,</p>
|
| 1177 |
|
|
<p>y => q0,</p>
|
| 1178 |
|
|
<p>wren => res,</p>
|
| 1179 |
|
|
<p>rowsel => in0,</p>
|
| 1180 |
|
|
<p>res => wren,</p>
|
| 1181 |
|
|
<p>x => c(13));</p>
|
| 1182 |
|
|
<p>mc147 : mc</p>
|
| 1183 |
|
|
<p>PORT MAP (</p>
|
| 1184 |
|
|
<p>vss => vss,</p>
|
| 1185 |
|
|
<p>vdd => vdd,</p>
|
| 1186 |
|
|
<p>y => q7,</p>
|
| 1187 |
|
|
<p>wren => res,</p>
|
| 1188 |
|
|
<p>rowsel => in7,</p>
|
| 1189 |
|
|
<p>res => wren,</p>
|
| 1190 |
|
|
<p>x => c(14));</p>
|
| 1191 |
|
|
<p>mc146 : mc</p>
|
| 1192 |
|
|
<p>PORT MAP (</p>
|
| 1193 |
|
|
<p>vss => vss,</p>
|
| 1194 |
|
|
<p>vdd => vdd,</p>
|
| 1195 |
|
|
<p>y => q6,</p>
|
| 1196 |
|
|
<p>wren => res,</p>
|
| 1197 |
|
|
<p>rowsel => in6,</p>
|
| 1198 |
|
|
<p>res => wren,</p>
|
| 1199 |
|
|
<p>x => c(14));</p>
|
| 1200 |
|
|
<p>mc145 : mc</p>
|
| 1201 |
|
|
<p>PORT MAP (</p>
|
| 1202 |
|
|
<p>vss => vss,</p>
|
| 1203 |
|
|
<p>vdd => vdd,</p>
|
| 1204 |
|
|
<p>y => q5,</p>
|
| 1205 |
|
|
<p>wren => res,</p>
|
| 1206 |
|
|
<p>rowsel => in5,</p>
|
| 1207 |
|
|
<p>res => wren,</p>
|
| 1208 |
|
|
<p>x => c(14));</p>
|
| 1209 |
|
|
<p>mc144 : mc</p>
|
| 1210 |
|
|
<p>PORT MAP (</p>
|
| 1211 |
|
|
<p>vss => vss,</p>
|
| 1212 |
|
|
<p>vdd => vdd,</p>
|
| 1213 |
|
|
<p>y => q4,</p>
|
| 1214 |
|
|
<p>wren => res,</p>
|
| 1215 |
|
|
<p>rowsel => in4,</p>
|
| 1216 |
|
|
<p>res => wren,</p>
|
| 1217 |
|
|
<p>x => c(14));</p>
|
| 1218 |
|
|
<p>mc143 : mc</p>
|
| 1219 |
|
|
<p>PORT MAP (</p>
|
| 1220 |
|
|
<p>vss => vss,</p>
|
| 1221 |
|
|
<p>vdd => vdd,</p>
|
| 1222 |
|
|
<p>y => q3,</p>
|
| 1223 |
|
|
<p>wren => res,</p>
|
| 1224 |
|
|
<p>rowsel => in3,</p>
|
| 1225 |
|
|
<p>res => wren,</p>
|
| 1226 |
|
|
<p>x => c(14));</p>
|
| 1227 |
|
|
<p>mc142 : mc</p>
|
| 1228 |
|
|
<p>PORT MAP (</p>
|
| 1229 |
|
|
<p>vss => vss,</p>
|
| 1230 |
|
|
<p>vdd => vdd,</p>
|
| 1231 |
|
|
<p>y => q2,</p>
|
| 1232 |
|
|
<p>wren => res,</p>
|
| 1233 |
|
|
<p>rowsel => in2,</p>
|
| 1234 |
|
|
<p>res => wren,</p>
|
| 1235 |
|
|
<p>x => c(14));</p>
|
| 1236 |
|
|
<p>mc141 : mc</p>
|
| 1237 |
|
|
<p>PORT MAP (</p>
|
| 1238 |
|
|
<p>vss => vss,</p>
|
| 1239 |
|
|
<p>vdd => vdd,</p>
|
| 1240 |
|
|
<p>y => q1,</p>
|
| 1241 |
|
|
<p>wren => res,</p>
|
| 1242 |
|
|
<p>rowsel => in1,</p>
|
| 1243 |
|
|
<p>res => wren,</p>
|
| 1244 |
|
|
<p>x => c(14));</p>
|
| 1245 |
|
|
<p>mc140 : mc</p>
|
| 1246 |
|
|
<p>PORT MAP (</p>
|
| 1247 |
|
|
<p>vss => vss,</p>
|
| 1248 |
|
|
<p>vdd => vdd,</p>
|
| 1249 |
|
|
<p>y => q0,</p>
|
| 1250 |
|
|
<p>wren => res,</p>
|
| 1251 |
|
|
<p>rowsel => in0,</p>
|
| 1252 |
|
|
<p>res => wren,</p>
|
| 1253 |
|
|
<p>x => c(14));</p>
|
| 1254 |
|
|
<p>mc157 : mc</p>
|
| 1255 |
|
|
<p>PORT MAP (</p>
|
| 1256 |
|
|
<p>vss => vss,</p>
|
| 1257 |
|
|
<p>vdd => vdd,</p>
|
| 1258 |
|
|
<p>y => q7,</p>
|
| 1259 |
|
|
<p>wren => res,</p>
|
| 1260 |
|
|
<p>rowsel => in7,</p>
|
| 1261 |
|
|
<p>res => wren,</p>
|
| 1262 |
|
|
<p>x => c(15));</p>
|
| 1263 |
|
|
<p>mc156 : mc</p>
|
| 1264 |
|
|
<p>PORT MAP (</p>
|
| 1265 |
|
|
<p>vss => vss,</p>
|
| 1266 |
|
|
<p>vdd => vdd,</p>
|
| 1267 |
|
|
<p>y => q6,</p>
|
| 1268 |
|
|
<p>wren => res,</p>
|
| 1269 |
|
|
<p>rowsel => in6,</p>
|
| 1270 |
|
|
<p>res => wren,</p>
|
| 1271 |
|
|
<p>x => c(15));</p>
|
| 1272 |
|
|
<p>mc155 : mc</p>
|
| 1273 |
|
|
<p>PORT MAP (</p>
|
| 1274 |
|
|
<p>vss => vss,</p>
|
| 1275 |
|
|
<p>vdd => vdd,</p>
|
| 1276 |
|
|
<p>y => q5,</p>
|
| 1277 |
|
|
<p>wren => res,</p>
|
| 1278 |
|
|
<p>rowsel => in5,</p>
|
| 1279 |
|
|
<p>res => wren,</p>
|
| 1280 |
|
|
<p>x => c(15));</p>
|
| 1281 |
|
|
<p>mc154 : mc</p>
|
| 1282 |
|
|
<p>PORT MAP (</p>
|
| 1283 |
|
|
<p>vss => vss,</p>
|
| 1284 |
|
|
<p>vdd => vdd,</p>
|
| 1285 |
|
|
<p>y => q4,</p>
|
| 1286 |
|
|
<p>wren => res,</p>
|
| 1287 |
|
|
<p>rowsel => in4,</p>
|
| 1288 |
|
|
<p>res => wren,</p>
|
| 1289 |
|
|
<p>x => c(15));</p>
|
| 1290 |
|
|
<p>mc153 : mc</p>
|
| 1291 |
|
|
<p>PORT MAP (</p>
|
| 1292 |
|
|
<p>vss => vss,</p>
|
| 1293 |
|
|
<p>vdd => vdd,</p>
|
| 1294 |
|
|
<p>y => q3,</p>
|
| 1295 |
|
|
<p>wren => res,</p>
|
| 1296 |
|
|
<p>rowsel => in3,</p>
|
| 1297 |
|
|
<p>res => wren,</p>
|
| 1298 |
|
|
<p>x => c(15));</p>
|
| 1299 |
|
|
<p>mc152 : mc</p>
|
| 1300 |
|
|
<p>PORT MAP (</p>
|
| 1301 |
|
|
<p>vss => vss,</p>
|
| 1302 |
|
|
<p>vdd => vdd,</p>
|
| 1303 |
|
|
<p>y => q2,</p>
|
| 1304 |
|
|
<p>wren => res,</p>
|
| 1305 |
|
|
<p>rowsel => in2,</p>
|
| 1306 |
|
|
<p>res => wren,</p>
|
| 1307 |
|
|
<p>x => c(15));</p>
|
| 1308 |
|
|
<p>mc151 : mc</p>
|
| 1309 |
|
|
<p>PORT MAP (</p>
|
| 1310 |
|
|
<p>vss => vss,</p>
|
| 1311 |
|
|
<p>vdd => vdd,</p>
|
| 1312 |
|
|
<p>y => q1,</p>
|
| 1313 |
|
|
<p>wren => res,</p>
|
| 1314 |
|
|
<p>rowsel => in1,</p>
|
| 1315 |
|
|
<p>res => wren,</p>
|
| 1316 |
|
|
<p>x => c(15));</p>
|
| 1317 |
|
|
<p>mc150 : mc</p>
|
| 1318 |
|
|
<p>PORT MAP (</p>
|
| 1319 |
|
|
<p>vss => vss,</p>
|
| 1320 |
|
|
<p>vdd => vdd,</p>
|
| 1321 |
|
|
<p>y => q0,</p>
|
| 1322 |
|
|
<p>wren => res,</p>
|
| 1323 |
|
|
<p>rowsel => in0,</p>
|
| 1324 |
|
|
<p>res => wren,</p>
|
| 1325 |
|
|
<p>x => c(15));</p>
|
| 1326 |
|
|
<p>bufo7 : p1_y</p>
|
| 1327 |
|
|
<p>PORT MAP (</p>
|
| 1328 |
|
|
<p>vss => vss,</p>
|
| 1329 |
|
|
<p>vdd => vdd,</p>
|
| 1330 |
|
|
<p>t => io7,</p>
|
| 1331 |
|
|
<p>i => q7);</p>
|
| 1332 |
|
|
<p>bufo6 : p1_y</p>
|
| 1333 |
|
|
<p>PORT MAP (</p>
|
| 1334 |
|
|
<p>vss => vss,</p>
|
| 1335 |
|
|
<p>vdd => vdd,</p>
|
| 1336 |
|
|
<p>t => io6,</p>
|
| 1337 |
|
|
<p>i => q6);</p>
|
| 1338 |
|
|
<p>bufo5 : p1_y</p>
|
| 1339 |
|
|
<p>PORT MAP (</p>
|
| 1340 |
|
|
<p>vss => vss,</p>
|
| 1341 |
|
|
<p>vdd => vdd,</p>
|
| 1342 |
|
|
<p>t => io5,</p>
|
| 1343 |
|
|
<p>i => q5);</p>
|
| 1344 |
|
|
<p>bufo4 : p1_y</p>
|
| 1345 |
|
|
<p>PORT MAP (</p>
|
| 1346 |
|
|
<p>vss => vss,</p>
|
| 1347 |
|
|
<p>vdd => vdd,</p>
|
| 1348 |
|
|
<p>t => io4,</p>
|
| 1349 |
|
|
<p>i => q4);</p>
|
| 1350 |
|
|
<p>bufo3 : p1_y</p>
|
| 1351 |
|
|
<p>PORT MAP (</p>
|
| 1352 |
|
|
<p>vss => vss,</p>
|
| 1353 |
|
|
<p>vdd => vdd,</p>
|
| 1354 |
|
|
<p>t => io3,</p>
|
| 1355 |
|
|
<p>i => q3);</p>
|
| 1356 |
|
|
<p>bufo2 : p1_y</p>
|
| 1357 |
|
|
<p>PORT MAP (</p>
|
| 1358 |
|
|
<p>vss => vss,</p>
|
| 1359 |
|
|
<p>vdd => vdd,</p>
|
| 1360 |
|
|
<p>t => io2,</p>
|
| 1361 |
|
|
<p>i => q2);</p>
|
| 1362 |
|
|
<p>bufo1 : p1_y</p>
|
| 1363 |
|
|
<p>PORT MAP (</p>
|
| 1364 |
|
|
<p>vss => vss,</p>
|
| 1365 |
|
|
<p>vdd => vdd,</p>
|
| 1366 |
|
|
<p>t => io1,</p>
|
| 1367 |
|
|
<p>i => q1);</p>
|
| 1368 |
|
|
<p>bufo0 : p1_y</p>
|
| 1369 |
|
|
<p>PORT MAP (</p>
|
| 1370 |
|
|
<p>vss => vss,</p>
|
| 1371 |
|
|
<p>vdd => vdd,</p>
|
| 1372 |
|
|
<p>t => io0,</p>
|
| 1373 |
|
|
<p>i => q0);</p>
|
| 1374 |
|
|
<p>end VST;</p>
|
| 1375 |
|
|
</font>
|
| 1376 |
|
|
|
| 1377 |
|
|
<b><font size=+1>Maintainers and Authors :</font></b>
|
| 1378 |
|
|
<p>LCD Driver development team
|
| 1379 |
|
|
<p>current members:
|
| 1380 |
|
|
|
| 1381 |
|
|
<ul>
|
| 1382 |
|
|
<li>
|
| 1383 |
|
|
<a href="mailto:marta@vlsi.itb.ac.id">Hendra Gunawan</a></li>
|
| 1384 |
|
|
|
| 1385 |
|
|
<li>
|
| 1386 |
|
|
<a href="mailto:sigit@students.ee.itb.ac.id">Nurhadi Wiyono</a></li>
|
| 1387 |
|
|
|
| 1388 |
|
|
<li>
|
| 1389 |
|
|
<a href="mailto:sigit@students.ee.itb.ac.id">Kharisma Sinung P</a></li>
|
| 1390 |
|
|
|
| 1391 |
|
|
</ul>
|
| 1392 |
|
|
|
| 1393 |
|
|
<p>
|
| 1394 |
|
|
<b><font size=+1>Mailing-list:</font></b>
|
| 1395 |
|
|
<ul><a href="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</a></ul>
|
| 1396 |
|
|
|
| 1397 |
|
|
|
| 1398 |
|
|
|
| 1399 |
|
|
|
| 1400 |
|
|
|
| 1401 |
|
|
|
| 1402 |
|
|
</td></tr></table>
|
| 1403 |
|
|
</td></tr>
|
| 1404 |
|
|
<tr><td bgcolor="#f8f8f0"> </td>
|
| 1405 |
|
|
<td valign="bottom">
|
| 1406 |
|
|
<table cellspacing=0 cellpadding=4 border=0 width="100%"bgcolor="#f0f0f0"><tr>
|
| 1407 |
|
|
<td align=left><i><small>Last modified on Sunday, 17-Sep-2000 03:58:04 JAVT</i></td>
|
| 1408 |
|
|
<td align=right><i><small>Copyright © 1999-2000 OPENCORES.ORG. All rights reserved.</td>
|
| 1409 |
|
|
</tr></table>
|
| 1410 |
|
|
|
| 1411 |
|
|
</td></tr></table>
|
| 1412 |
|
|
|
| 1413 |
|
|
</td></tr></table>
|
| 1414 |
|
|
|
| 1415 |
|
|
</body></html>
|
