URL
https://opencores.org/ocsvn/lcd_to_hdmi_output_ip/lcd_to_hdmi_output_ip/trunk
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
4 |
morgothcre |
# Verilog HDMI output IP.
|
| 2 |
|
|
|
| 3 |
|
|
This is a very simple HDMI output IP that is driven by a LCD IP.
|
| 4 |
|
|
|
| 5 |
|
|
Is accepting RGB 8 bit/color vertical and horizontal synchronization, data enable and a reference clock that is 5x the LCD clock.
|
| 6 |
|
|
The outputs are the three serial channels the clock channel and the LCD clock that is equal to reference clock / 5.
|
| 7 |
|
|
|
| 8 |
|
|
The LCD clock provided by the HDMI IP is used to clocking the LCD IP.
|
| 9 |
|
|
|
| 10 |
|
|
The RGB and sinchronization signals are provided by an LCD IP.
|
| 11 |
|
|
|
| 12 |
|
|
The maximum obtained resolution is 1440x900 at less that 60 Hz, maximum 1 gigabit/second/line for Artix7 -1 grade device.
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
