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[/] [light8080/] [trunk/] [vhdl/] [demos/] [4kbasic/] [rs232_rx.vhdl] - Blame information for rev 82

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1 82 ja_rd 
--##############################################################################
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-- RS-232 receiver, parametrizable bit rate through generics.
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-- Bit rate defaults to 19200 bps @50MHz.
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-- WARNING: Hacked up for light8080 demo. Poor performance, no formal testing!
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-- I don't advise using this in for any general purpose.
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--##############################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity rs232_rx is
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  generic (
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    BAUD_RATE     : integer := 19200;
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    CLOCK_FREQ    : integer := 50000000);
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    port (
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        rxd       : in std_logic;
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        data_rx   : out std_logic_vector(7 downto 0);
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        rx_rdy    : out std_logic;
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        read_rx   : in std_logic;
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        clk       : in std_logic;
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        reset     : in std_logic);
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end rs232_rx;
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architecture hardwired of rs232_rx is
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-- Bit sampling period is 1/16 of the baud rate
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constant SAMPLING_PERIOD : integer := (CLOCK_FREQ / BAUD_RATE) / 16;
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--##############################################################################
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-- Serial port signals
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signal rxd_q :            std_logic;
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signal tick_ctr :         std_logic_vector(3 downto 0);
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signal state :            std_logic_vector(3 downto 0);
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signal next_state :       std_logic_vector(3 downto 0);
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signal start_bit_detected : std_logic;
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signal reset_tick_ctr :   std_logic;
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signal stop_bit_sampled : std_logic;
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signal load_rx_buffer :   std_logic;
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signal stop_error :       std_logic;
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signal samples :          std_logic_vector(2 downto 0);
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signal sampled_bit :      std_logic;
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signal do_shift :         std_logic;
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signal rx_buffer :        std_logic_vector(7 downto 0);
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signal rx_shift_reg :     std_logic_vector(9 downto 0);
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signal tick_ctr_enable :  std_logic;
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signal tick_baud_ctr :    std_logic_vector(10 downto 0);
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signal rx_rdy_flag :      std_logic;
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signal set_rx_rdy_flag :  std_logic;
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begin
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process(clk)
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begin
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  if clk'event and clk='1' then
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    if reset='1' then
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      tick_baud_ctr <= (others => '0');
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    else
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      if conv_integer(tick_baud_ctr)=SAMPLING_PERIOD then -- 325 for 9600 bps
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        tick_baud_ctr <= (others => '0');
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      else
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        tick_baud_ctr <= tick_baud_ctr + 1;
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      end if;
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    end if;
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  end if;
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end process;
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tick_ctr_enable<= '1' when conv_integer(tick_baud_ctr)=SAMPLING_PERIOD else '0';
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process(clk)
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begin
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  if clk'event and clk='1' then
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    if reset='1' then
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      rxd_q <= '0';
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    else
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      if tick_ctr_enable='1' then
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        rxd_q <= rxd;
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      end if;
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    end if;
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  end if;
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end process;
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start_bit_detected <= '1' when state="0000" and rxd_q='1' and rxd='0' else '0';
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reset_tick_ctr <= '1' when start_bit_detected='1' else '0';
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stop_bit_sampled <= '1' when state="1010" and tick_ctr="1011" else '0';
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load_rx_buffer <= '1' when stop_bit_sampled='1' and sampled_bit='1' else '0';
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stop_error <= '1' when stop_bit_sampled='1' and sampled_bit='0' else '0';
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process(clk)
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begin
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  if clk'event and clk='1' then
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    if reset='1' then
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      tick_ctr <= "0000";
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    else
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      if tick_ctr_enable='1' then
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        if tick_ctr="1111" or reset_tick_ctr='1' then
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          tick_ctr <= "0000";
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        else
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          tick_ctr <= tick_ctr + 1;
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        end if;
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      end if;
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    end if;
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  end if;
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end process;
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next_state <=
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  "0001" when state="0000" and start_bit_detected='1' else
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  "0000" when state="0001" and tick_ctr="1010" and sampled_bit='1' else
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  "0000" when state="1010" and tick_ctr="1111" else
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  state + 1 when tick_ctr="1111" and do_shift='1' else
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  state;
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process(clk)
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begin
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  if clk'event and clk='1' then
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    if reset='1' then
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      state <= "0000";
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    else
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      if tick_ctr_enable='1' then
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        state <= next_state;
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      end if;
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    end if;
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  end if;
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end process;
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process(clk)
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begin
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  if clk'event and clk='1' then
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    if reset='1' then
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      samples <= "000";
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    else
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      if tick_ctr_enable='1' then
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        if tick_ctr="0111" then
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          samples(0) <= rxd;
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        end if;
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        if tick_ctr="1000" then
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          samples(1) <= rxd;
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        end if;
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        if tick_ctr="1001" then
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          samples(2) <= rxd;
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        end if;
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      end if;
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    end if;
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  end if;
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end process;
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with samples select
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  sampled_bit <=  '0' when "000",
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                  '0' when "001",
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                  '0' when "010",
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                  '1' when "011",
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                  '0' when "100",
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                  '1' when "101",
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                  '1' when "110",
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                  '1' when others;
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process(clk)
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begin
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  if clk'event and clk='1' then
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    if reset='1' then
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      rx_buffer <= "00000000";
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      set_rx_rdy_flag <= '0';
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    else
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      if tick_ctr_enable='1' and load_rx_buffer='1' and rx_rdy_flag='0' then
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        rx_buffer <= rx_shift_reg(8 downto 1);
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        set_rx_rdy_flag <= '1';
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      else
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        set_rx_rdy_flag <= '0';
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      end if;
180 
    end if;
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  end if;
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end process;
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process(clk)
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begin
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  if clk'event and clk='1' then
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    if reset='1' then
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      rx_rdy_flag <= '0';
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    else
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      if set_rx_rdy_flag='1' then
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        rx_rdy_flag <= '1';
192 
      else
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        if read_rx = '1' then
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          rx_rdy_flag <= '0';
195 
        end if;
196 
      end if;
197 
    end if;
198 
  end if;
199 
end process;
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do_shift <= state(0) or state(1) or state(2) or state(3);
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-- reception shift register
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process(clk)
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begin
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  if clk'event and clk='1' then
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    if reset='1' then
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      rx_shift_reg <= "1111111111";
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    else
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      if tick_ctr_enable='1' then
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        if tick_ctr="1010" and do_shift='1' then
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          rx_shift_reg(9) <= sampled_bit;
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          rx_shift_reg(8 downto 0) <= rx_shift_reg(9 downto 1);
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        end if;
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      end if;
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    end if;
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  end if;
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end process;
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rx_rdy <= rx_rdy_flag;
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data_rx <= rx_buffer;
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end hardwired;

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