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[/] [light8080/] [trunk/] [vhdl/] [demos/] [4kbasic/] [rs232_tx.vhdl] - Blame information for rev 82

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Line No. Rev Author Line
1 82 ja_rd
--##############################################################################
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-- RS-232 transmitter, parametrizable bit rate through generics.
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-- Bit rate defaults to 19200 bps @50MHz.
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-- WARNING: Hacked up for light8080 demo. Poor performance, no formal testing!
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-- I don't advise using this in for any general purpose.
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--##############################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity rs232_tx is
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  generic (
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    BAUD_RATE     : integer := 19200;
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    CLOCK_FREQ    : integer := 50000000);
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  port (
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      clk         : in std_logic;
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      reset       : in std_logic;
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      rdy         : out std_logic;
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      load        : in std_logic;
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      data_i      : in std_logic_vector(7 downto 0);
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      txd         : out std_logic);
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end rs232_tx;
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architecture hardwired of rs232_tx is
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-- Bit period expressed in master clock cycles
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constant BIT_PERIOD : integer := (CLOCK_FREQ / BAUD_RATE);
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signal counter :      std_logic_vector(13 downto 0);
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signal data :         std_logic_vector(10 downto 0);
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signal ctr_bit :      std_logic_vector(3 downto 0);
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signal tx :           std_logic;
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begin
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process(clk)
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begin
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if clk'event and clk='1' then
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  if reset='1' then
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    data <= "10111111111";
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    tx <= '0';
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    ctr_bit <= "0000";
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    counter <= (others => '0');
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  elsif load='1' and tx='0' then
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    data <= "1"&data_i&"01";
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    tx <= '1';
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  else
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    if tx='1' then
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      if conv_integer(counter) = BIT_PERIOD then --e.g. 5200 for 9600 bps
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        counter <= (others => '0');
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        data(9 downto 0) <= data(10 downto 1);
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        data(10) <= '1';
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        if ctr_bit = "1010" then
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           tx <= '0';
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           ctr_bit <= "0000";
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        else
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           ctr_bit <= ctr_bit + 1;
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        end if;
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      else
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        counter <= counter + 1;
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      end if;
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    end if;
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  end if;
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end if;
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end process;
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rdy <= not tx;
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txd <= data(0);
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end hardwired;

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