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[/] [linkruncca/] [trunk/] [src/] [window.v] - Blame information for rev 2

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module window(clk,datavalid,pix_in_current,pix_in_previous,A,B,C,D);
 
input clk,datavalid,pix_in_current,pix_in_previous;
output reg A,B,C,D;
 
always@(posedge clk)
        if(datavalid)begin
                A<=B;B<=pix_in_previous;
                C<=D;D<=pix_in_current;
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	jaytang	`module window(clk,datavalid,pix_in_current,pix_in_previous,A,B,C,D);`
2
3			`input clk,datavalid,pix_in_current,pix_in_previous;`
4			`output reg A,B,C,D;`
5
6			`always@(posedge clk)`
7			`if(datavalid)begin`
8			`A<=B;B<=pix_in_previous;`
9			`C<=D;D<=pix_in_current;`
10			`end`
11
12			`endmodule`

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[/] [linkruncca/] [trunk/] [src/] [window.v] - Blame information for rev 2