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[/] [loadbalancer/] [trunk/] [Balance/] [balance_top.vhd] - Blame information for rev 2

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--------------------------------------------------------
 
        LIBRARY IEEE;
        USE IEEE.STD_LOGIC_1164.ALL;
        use IEEE.std_logic_arith.all;
-------------------------------
        ENTITY balance_top IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
        SIGNAL          in_data                         :       IN      STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
        SIGNAL          in_ctrl                         :       IN      STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
    SIGNAL              in_wr                           :       IN              STD_LOGIC       ;
        SIGNAL          in_rdy                          :       OUT     STD_LOGIC       ;
 
        SIGNAL          out_data                        :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
        SIGNAL          out_ctrl                        :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
        SIGNAL          out_wr                          :       OUT     STD_LOGIC       ;
        SIGNAL          out_rdy                         :       IN              STD_LOGIC       ;
 
 
        SIGNAL          in_next_mac :IN   STD_LOGIC_VECTOR(47 DOWNTO 0);
        SIGNAL          in_exit_port :IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
        SIGNAL          in_next_mac_rdy : IN STD_LOGIC;
        SIGNAL          out_rd_next_mac : OUT STD_LOGIC;
        SIGNAL          key :OUT   STD_LOGIC_VECTOR(11 DOWNTO 0);
 
    --- Misc
    SIGNAL     en : IN STD_LOGIC;
    SIGNAL              reset                           :       IN              STD_LOGIC       ;
    SIGNAL              clk                             :       IN              STD_LOGIC
        );
        END ENTITY;
 
 ------------------------------------------------------
        ARCHITECTURE behavior OF balance_top IS
-------COMPONENET SMALL FIFO
                COMPONENT  small_fifo IS
        GENERIC(WIDTH :INTEGER := 72;
                        MAX_DEPTH_BITS :INTEGER := 3);
        PORT(
 
 
     SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input [WIDTH-1:0] din,     // Data in
     SIGNAL wr_en : IN STD_LOGIC;--input          wr_en,   // Write enable
 
     SIGNAL rd_en : IN STD_LOGIC;--input          rd_en,   // Read the next word 
 
     SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
     SIGNAL full : OUT STD_LOGIC;--output         full,
     SIGNAL nearly_full : OUT STD_LOGIC;--output         nearly_full,
     SIGNAL empty : OUT STD_LOGIC;--output         empty,
 
 
    SIGNAL reset :IN STD_LOGIC;
    SIGNAL clk   :IN STD_LOGIC
 
        );
        END COMPONENT;
-------COMPONENET SMALL FIFO
        COMPONENT  balance IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
 
                        SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
                        SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                        SIGNAL in_wr :IN STD_LOGIC;
                        SIGNAL in_rdy : OUT STD_LOGIC;
 
                        SIGNAL out_data : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
                        SIGNAL out_ctrl : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
                        SIGNAL out_wr : OUT STD_LOGIC;
                        SIGNAL out_rdy : IN STD_LOGIC;
 
                        SIGNAL in_next_mac :IN   STD_LOGIC_VECTOR(47 DOWNTO 0);
                        SIGNAL in_exit_port :IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
                        SIGNAL in_next_mac_rdy : IN STD_LOGIC;
                        SIGNAL out_rd_next_mac : OUT STD_LOGIC;
                        SIGNAL key :OUT   STD_LOGIC_VECTOR(11 DOWNTO 0);
 
                   SIGNAL reset :IN STD_LOGIC;
                   SIGNAL clk   :IN STD_LOGIC
 
        );
        END COMPONENT;
------------ one hot encoding state definition
 
        TYPE state_type IS (IDLE, IN_MODULE_HDRS,SKIP_HDRS, IN_PACKET, DUMP_1,DUMP_2,DUMP_3);
        ATTRIBUTE enum_encoding: STRING;
        ATTRIBUTE enum_encoding of state_type : type is "onehot";
 
        SIGNAL state, state_NEXT : state_type;
 
------------end state machine definition
 
----------------------FIFO        
          SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
          SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);
          SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_rd_en : STD_LOGIC;
          SIGNAL in_fifo_rd_en_p : STD_LOGIC;
          SIGNAL in_fifo_go : STD_LOGIC;
          SIGNAL in_fifo_go_i : STD_LOGIC;
      SIGNAL in_fifo_dout  : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_full : STD_LOGIC;
      SIGNAL in_fifo_nearly_full : STD_LOGIC;
      SIGNAL in_fifo_empty : STD_LOGIC;
                 SIGNAL wr_en : STD_LOGIC;
          SIGNAL                out_data_i                      :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
          SIGNAL                out_ctrl_i                      :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
          SIGNAL                out_wr_i                        :               STD_LOGIC       ;
          SIGNAL                out_rdy_int                     :               STD_LOGIC       ;
---------------------------------------------------
        BEGIN
 
        ------PORT MAP open_header
 
                -------PORT MAP SMALL FIFO DATA
                small_fifo_Inst :  small_fifo
        GENERIC MAP(WIDTH  => 72,
                        MAX_DEPTH_BITS  => 5)
        PORT MAP(
 
 
      din =>(in_fifo_in),
      wr_en =>wr_en,
 
      rd_en => in_fifo_rd_en,
 
      dout =>in_fifo_dout,
      full =>in_fifo_full,
      nearly_full =>in_fifo_nearly_full,
      empty => in_fifo_empty,
 
 
     reset => reset ,
     clk  => clk
 
        );
 
 
-------PORT MAP SMALL FIFO
--      int2ext_inst :  int2ext 
--      GENERIC MAP(DATA_WIDTH => 64,
--                      CTRL_WIDTH => 8)
--      PORT MAP(
--                              in_data                            => out_data_i,
--                              in_ctrl                            => out_ctrl_i,
--                              in_wr                           => out_wr_i,
--                              in_rdy                          => out_rdy_int,
--              
--                              out_data                        => out_data,
--                              out_ctrl                        => out_ctrl,
--                              out_wr                          => out_wr,
--                              out_rdy                            => out_rdy,
--                              reset                           => reset,
--                              clk                             => clk
--      );
--      
                balance_Inst :  balance
        GENERIC MAP (DATA_WIDTH => 64,
                        CTRL_WIDTH => 8)
        PORT MAP (
                                 in_data                           => out_data_i,
                                 in_ctrl                           => out_ctrl_i,
                                 in_wr                                  => out_wr_i,
                                 in_rdy                                         => out_rdy_int,
 
                                 out_data                               => out_data,
                                 out_ctrl                               => out_ctrl,
                                 out_wr                                         => out_wr,
                                 out_rdy                                => out_rdy,
 
                           in_next_mac                  => in_next_mac,
                           in_exit_port                         =>      in_exit_port,
                           in_next_mac_rdy              => in_next_mac_rdy,
                           out_rd_next_mac              => out_rd_next_mac,
                           key                                          => key,
 
                      reset                                     => reset,
                      clk                                       =>clk
 
        );
-----------------------
      in_fifo_in <=     in_data & in_ctrl ;
                wr_en <= en and in_wr;
                fifo_data       <=         in_fifo_dout(71 DOWNTO 8)    ;
                fifo_ctrl       <=      in_fifo_dout(7 DOWNTO 0) ;
                in_fifo_rd_en <=  out_rdy_int and(not in_fifo_empty) ;
 
 
 
                 in_rdy         <=      (NOT in_fifo_nearly_full);-- or (not en)        ;
 
 
 
 
 
PROCESS(clk,reset)
BEGIN
        IF (reset ='1') THEN
                state <=IDLE;
                ELSIF clk'EVENT AND clk ='1' THEN
                state<=state_next;
                in_fifo_rd_en_p <= in_fifo_rd_en;
        END IF;
END PROCESS;
                PROCESS(clk,reset)
                BEGIN
 
                        IF clk'EVENT AND clk ='1' THEN
                                                                        out_data_i                              <=      fifo_data;
                                                                        out_ctrl_i                              <=      fifo_ctrl;
                                                                        out_wr_i                                   <=   in_fifo_rd_en_p ;
                                                END IF;
                END PROCESS;
 
---------------Register output
--              PROCESS(clk,reset)
--              BEGIN
--                      
--                      IF clk'EVENT AND clk ='1' THEN
--                                                                      out_data                                <=      out_data_i;
--                                                                      out_ctrl                                <=      out_ctrl_i;
--                                                                      out_wr                              <=  out_wr_i;       
--                                                                      
--                      END IF;
--              END PROCESS;    
END behavior;
 

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Subversion Repositories loadbalancer

[/] [loadbalancer/] [trunk/] [Balance/] [balance_top.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	atalla	`--------------------------------------------------------`
2
3			`LIBRARY IEEE;`
4			`USE IEEE.STD_LOGIC_1164.ALL;`
5			`use IEEE.std_logic_arith.all;`
6			`-------------------------------`
7			`ENTITY balance_top IS`
8			`GENERIC(DATA_WIDTH :INTEGER := 64;`
9			`CTRL_WIDTH :INTEGER := 8);`
10			`PORT(`
11			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
12			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
13			`SIGNAL in_wr : IN STD_LOGIC ;`
14			`SIGNAL in_rdy : OUT STD_LOGIC ;`
15
16			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
17			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
18			`SIGNAL out_wr : OUT STD_LOGIC ;`
19			`SIGNAL out_rdy : IN STD_LOGIC ;`
20
21
22			`SIGNAL in_next_mac :IN STD_LOGIC_VECTOR(47 DOWNTO 0);`
23			`SIGNAL in_exit_port :IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
24			`SIGNAL in_next_mac_rdy : IN STD_LOGIC;`
25			`SIGNAL out_rd_next_mac : OUT STD_LOGIC;`
26			`SIGNAL key :OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
27
28			`--- Misc`
29			`SIGNAL en : IN STD_LOGIC;`
30			`SIGNAL reset : IN STD_LOGIC ;`
31			`SIGNAL clk : IN STD_LOGIC`
32			`);`
33			`END ENTITY;`
34
35			`------------------------------------------------------`
36			`ARCHITECTURE behavior OF balance_top IS`
37			`-------COMPONENET SMALL FIFO`
38			`COMPONENT small_fifo IS`
39			`GENERIC(WIDTH :INTEGER := 72;`
40			`MAX_DEPTH_BITS :INTEGER := 3);`
41			`PORT(`
42
43
44			`SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input [WIDTH-1:0] din, // Data in`
45			`SIGNAL wr_en : IN STD_LOGIC;--input wr_en, // Write enable`
46
47			`SIGNAL rd_en : IN STD_LOGIC;--input rd_en, // Read the next word`
48
49			`SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output reg [WIDTH-1:0] dout, // Data out`
50			`SIGNAL full : OUT STD_LOGIC;--output full,`
51			`SIGNAL nearly_full : OUT STD_LOGIC;--output nearly_full,`
52			`SIGNAL empty : OUT STD_LOGIC;--output empty,`
53
54
55			`SIGNAL reset :IN STD_LOGIC;`
56			`SIGNAL clk :IN STD_LOGIC`
57
58			`);`
59			`END COMPONENT;`
60			`-------COMPONENET SMALL FIFO`
61			`COMPONENT balance IS`
62			`GENERIC(DATA_WIDTH :INTEGER := 64;`
63			`CTRL_WIDTH :INTEGER := 8);`
64			`PORT(`
65
66			`SIGNAL in_data :IN STD_LOGIC_VECTOR(63 DOWNTO 0);`
67			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
68			`SIGNAL in_wr :IN STD_LOGIC;`
69			`SIGNAL in_rdy : OUT STD_LOGIC;`
70
71			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);`
72			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
73			`SIGNAL out_wr : OUT STD_LOGIC;`
74			`SIGNAL out_rdy : IN STD_LOGIC;`
75
76			`SIGNAL in_next_mac :IN STD_LOGIC_VECTOR(47 DOWNTO 0);`
77			`SIGNAL in_exit_port :IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
78			`SIGNAL in_next_mac_rdy : IN STD_LOGIC;`
79			`SIGNAL out_rd_next_mac : OUT STD_LOGIC;`
80			`SIGNAL key :OUT STD_LOGIC_VECTOR(11 DOWNTO 0);`
81
82			`SIGNAL reset :IN STD_LOGIC;`
83			`SIGNAL clk :IN STD_LOGIC`
84
85			`);`
86			`END COMPONENT;`
87			`------------ one hot encoding state definition`
88
89			`TYPE state_type IS (IDLE, IN_MODULE_HDRS,SKIP_HDRS, IN_PACKET, DUMP_1,DUMP_2,DUMP_3);`
90			`ATTRIBUTE enum_encoding: STRING;`
91			`ATTRIBUTE enum_encoding of state_type : type is "onehot";`
92
93			`SIGNAL state, state_NEXT : state_type;`
94
95			`------------end state machine definition`
96
97			`----------------------FIFO`
98			`SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);`
99			`SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);`
100			`SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);`
101			`SIGNAL in_fifo_rd_en : STD_LOGIC;`
102			`SIGNAL in_fifo_rd_en_p : STD_LOGIC;`
103			`SIGNAL in_fifo_go : STD_LOGIC;`
104			`SIGNAL in_fifo_go_i : STD_LOGIC;`
105			`SIGNAL in_fifo_dout : STD_LOGIC_VECTOR(71 DOWNTO 0);`
106			`SIGNAL in_fifo_full : STD_LOGIC;`
107			`SIGNAL in_fifo_nearly_full : STD_LOGIC;`
108			`SIGNAL in_fifo_empty : STD_LOGIC;`
109			`SIGNAL wr_en : STD_LOGIC;`
110			`SIGNAL out_data_i : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
111			`SIGNAL out_ctrl_i : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
112			`SIGNAL out_wr_i : STD_LOGIC ;`
113			`SIGNAL out_rdy_int : STD_LOGIC ;`
114			`---------------------------------------------------`
115			`BEGIN`
116
117			`------PORT MAP open_header`
118
119			`-------PORT MAP SMALL FIFO DATA`
120			`small_fifo_Inst : small_fifo`
121			`GENERIC MAP(WIDTH => 72,`
122			`MAX_DEPTH_BITS => 5)`
123			`PORT MAP(`
124
125
126			`din =>(in_fifo_in),`
127			`wr_en =>wr_en,`
128
129			`rd_en => in_fifo_rd_en,`
130
131			`dout =>in_fifo_dout,`
132			`full =>in_fifo_full,`
133			`nearly_full =>in_fifo_nearly_full,`
134			`empty => in_fifo_empty,`
135
136
137			`reset => reset ,`
138			`clk => clk`
139
140			`);`
141
142
143			`-------PORT MAP SMALL FIFO`
144			`-- int2ext_inst : int2ext`
145			`-- GENERIC MAP(DATA_WIDTH => 64,`
146			`-- CTRL_WIDTH => 8)`
147			`-- PORT MAP(`
148			`-- in_data => out_data_i,`
149			`-- in_ctrl => out_ctrl_i,`
150			`-- in_wr => out_wr_i,`
151			`-- in_rdy => out_rdy_int,`
152			`--`
153			`-- out_data => out_data,`
154			`-- out_ctrl => out_ctrl,`
155			`-- out_wr => out_wr,`
156			`-- out_rdy => out_rdy,`
157			`-- reset => reset,`
158			`-- clk => clk`
159			`-- );`
160			`--`
161			`balance_Inst : balance`
162			`GENERIC MAP (DATA_WIDTH => 64,`
163			`CTRL_WIDTH => 8)`
164			`PORT MAP (`
165			`in_data => out_data_i,`
166			`in_ctrl => out_ctrl_i,`
167			`in_wr => out_wr_i,`
168			`in_rdy => out_rdy_int,`
169
170			`out_data => out_data,`
171			`out_ctrl => out_ctrl,`
172			`out_wr => out_wr,`
173			`out_rdy => out_rdy,`
174
175			`in_next_mac => in_next_mac,`
176			`in_exit_port => in_exit_port,`
177			`in_next_mac_rdy => in_next_mac_rdy,`
178			`out_rd_next_mac => out_rd_next_mac,`
179			`key => key,`
180
181			`reset => reset,`
182			`clk =>clk`
183
184			`);`
185			`-----------------------`
186			`in_fifo_in <= in_data & in_ctrl ;`
187			`wr_en <= en and in_wr;`
188			`fifo_data <= in_fifo_dout(71 DOWNTO 8) ;`
189			`fifo_ctrl <= in_fifo_dout(7 DOWNTO 0) ;`
190			`in_fifo_rd_en <= out_rdy_int and(not in_fifo_empty) ;`
191
192
193
194			`in_rdy <= (NOT in_fifo_nearly_full);-- or (not en) ;`
195
196
197
198
199
200			`PROCESS(clk,reset)`
201			`BEGIN`
202			`IF (reset ='1') THEN`
203			`state <=IDLE;`
204			`ELSIF clk'EVENT AND clk ='1' THEN`
205			`state<=state_next;`
206			`in_fifo_rd_en_p <= in_fifo_rd_en;`
207			`END IF;`
208			`END PROCESS;`
209			`PROCESS(clk,reset)`
210			`BEGIN`
211
212			`IF clk'EVENT AND clk ='1' THEN`
213			`out_data_i <= fifo_data;`
214			`out_ctrl_i <= fifo_ctrl;`
215			`out_wr_i <= in_fifo_rd_en_p ;`
216			`END IF;`
217			`END PROCESS;`
218
219			`---------------Register output`
220			`-- PROCESS(clk,reset)`
221			`-- BEGIN`
222			`--`
223			`-- IF clk'EVENT AND clk ='1' THEN`
224			`-- out_data <= out_data_i;`
225			`-- out_ctrl <= out_ctrl_i;`
226			`-- out_wr <= out_wr_i;`
227			`--`
228			`-- END IF;`
229			`-- END PROCESS;`
230			`END behavior;`
231