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--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=5 WIDTHAD_B=5 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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--VERSION_BEGIN 7.2SP3 cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ VERSION_END
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-- Copyright (C) 1991-2007 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
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WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
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RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = ram_bits (AUTO) 256
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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SUBDESIGN altsyncram_9ni1
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(
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address_a[4..0] : input;
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address_b[4..0] : input;
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clock0 : input;
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data_a[7..0] : input;
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q_b[7..0] : output;
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wren_a : input;
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)
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VARIABLE
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ram_block1a0 : stratixii_ram_block
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WITH (
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CONNECTIVITY_CHECKING = "OFF",
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DONT_POWER_OPTIMIZE = "ON",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 5,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 0,
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PORT_A_LAST_ADDRESS = 31,
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PORT_A_LOGICAL_RAM_DEPTH = 32,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 5,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_OUT_CLOCK = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 0,
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PORT_B_LAST_ADDRESS = 31,
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PORT_B_LOGICAL_RAM_DEPTH = 32,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a1 : stratixii_ram_block
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WITH (
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CONNECTIVITY_CHECKING = "OFF",
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DONT_POWER_OPTIMIZE = "ON",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 5,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 1,
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PORT_A_LAST_ADDRESS = 31,
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PORT_A_LOGICAL_RAM_DEPTH = 32,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 5,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_OUT_CLOCK = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 1,
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PORT_B_LAST_ADDRESS = 31,
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PORT_B_LOGICAL_RAM_DEPTH = 32,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a2 : stratixii_ram_block
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WITH (
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| 99 |
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CONNECTIVITY_CHECKING = "OFF",
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DONT_POWER_OPTIMIZE = "ON",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 5,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 2,
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PORT_A_LAST_ADDRESS = 31,
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PORT_A_LOGICAL_RAM_DEPTH = 32,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 5,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_OUT_CLOCK = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 2,
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PORT_B_LAST_ADDRESS = 31,
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PORT_B_LOGICAL_RAM_DEPTH = 32,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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| 126 |
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);
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ram_block1a3 : stratixii_ram_block
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WITH (
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| 129 |
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CONNECTIVITY_CHECKING = "OFF",
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DONT_POWER_OPTIMIZE = "ON",
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| 131 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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| 133 |
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OPERATION_MODE = "dual_port",
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| 134 |
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PORT_A_ADDRESS_WIDTH = 5,
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| 135 |
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PORT_A_DATA_WIDTH = 1,
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| 136 |
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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| 137 |
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PORT_A_FIRST_ADDRESS = 0,
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| 138 |
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PORT_A_FIRST_BIT_NUMBER = 3,
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| 139 |
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PORT_A_LAST_ADDRESS = 31,
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| 140 |
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PORT_A_LOGICAL_RAM_DEPTH = 32,
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| 141 |
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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| 142 |
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PORT_B_ADDRESS_CLOCK = "clock0",
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| 143 |
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PORT_B_ADDRESS_WIDTH = 5,
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| 144 |
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PORT_B_DATA_OUT_CLEAR = "none",
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| 145 |
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PORT_B_DATA_OUT_CLOCK = "none",
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| 146 |
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PORT_B_DATA_WIDTH = 1,
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| 147 |
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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| 148 |
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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| 149 |
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PORT_B_FIRST_ADDRESS = 0,
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| 150 |
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PORT_B_FIRST_BIT_NUMBER = 3,
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| 151 |
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PORT_B_LAST_ADDRESS = 31,
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| 152 |
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PORT_B_LOGICAL_RAM_DEPTH = 32,
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| 153 |
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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| 154 |
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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| 155 |
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RAM_BLOCK_TYPE = "AUTO"
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| 156 |
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);
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| 157 |
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ram_block1a4 : stratixii_ram_block
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| 158 |
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WITH (
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| 159 |
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CONNECTIVITY_CHECKING = "OFF",
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| 160 |
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DONT_POWER_OPTIMIZE = "ON",
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| 161 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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| 162 |
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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| 163 |
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OPERATION_MODE = "dual_port",
|
| 164 |
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PORT_A_ADDRESS_WIDTH = 5,
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| 165 |
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PORT_A_DATA_WIDTH = 1,
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| 166 |
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 167 |
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PORT_A_FIRST_ADDRESS = 0,
|
| 168 |
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PORT_A_FIRST_BIT_NUMBER = 4,
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| 169 |
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PORT_A_LAST_ADDRESS = 31,
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| 170 |
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PORT_A_LOGICAL_RAM_DEPTH = 32,
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| 171 |
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PORT_A_LOGICAL_RAM_WIDTH = 8,
|
| 172 |
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PORT_B_ADDRESS_CLOCK = "clock0",
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| 173 |
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PORT_B_ADDRESS_WIDTH = 5,
|
| 174 |
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PORT_B_DATA_OUT_CLEAR = "none",
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| 175 |
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PORT_B_DATA_OUT_CLOCK = "none",
|
| 176 |
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PORT_B_DATA_WIDTH = 1,
|
| 177 |
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 178 |
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 179 |
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PORT_B_FIRST_ADDRESS = 0,
|
| 180 |
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PORT_B_FIRST_BIT_NUMBER = 4,
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| 181 |
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PORT_B_LAST_ADDRESS = 31,
|
| 182 |
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PORT_B_LOGICAL_RAM_DEPTH = 32,
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| 183 |
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PORT_B_LOGICAL_RAM_WIDTH = 8,
|
| 184 |
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
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| 185 |
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RAM_BLOCK_TYPE = "AUTO"
|
| 186 |
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);
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| 187 |
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ram_block1a5 : stratixii_ram_block
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| 188 |
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WITH (
|
| 189 |
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CONNECTIVITY_CHECKING = "OFF",
|
| 190 |
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DONT_POWER_OPTIMIZE = "ON",
|
| 191 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 192 |
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MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 193 |
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OPERATION_MODE = "dual_port",
|
| 194 |
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PORT_A_ADDRESS_WIDTH = 5,
|
| 195 |
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PORT_A_DATA_WIDTH = 1,
|
| 196 |
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 197 |
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PORT_A_FIRST_ADDRESS = 0,
|
| 198 |
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PORT_A_FIRST_BIT_NUMBER = 5,
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| 199 |
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PORT_A_LAST_ADDRESS = 31,
|
| 200 |
|
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PORT_A_LOGICAL_RAM_DEPTH = 32,
|
| 201 |
|
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PORT_A_LOGICAL_RAM_WIDTH = 8,
|
| 202 |
|
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PORT_B_ADDRESS_CLOCK = "clock0",
|
| 203 |
|
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PORT_B_ADDRESS_WIDTH = 5,
|
| 204 |
|
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PORT_B_DATA_OUT_CLEAR = "none",
|
| 205 |
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PORT_B_DATA_OUT_CLOCK = "none",
|
| 206 |
|
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PORT_B_DATA_WIDTH = 1,
|
| 207 |
|
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 208 |
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 209 |
|
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PORT_B_FIRST_ADDRESS = 0,
|
| 210 |
|
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PORT_B_FIRST_BIT_NUMBER = 5,
|
| 211 |
|
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PORT_B_LAST_ADDRESS = 31,
|
| 212 |
|
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PORT_B_LOGICAL_RAM_DEPTH = 32,
|
| 213 |
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PORT_B_LOGICAL_RAM_WIDTH = 8,
|
| 214 |
|
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 215 |
|
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RAM_BLOCK_TYPE = "AUTO"
|
| 216 |
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);
|
| 217 |
|
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ram_block1a6 : stratixii_ram_block
|
| 218 |
|
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WITH (
|
| 219 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 220 |
|
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DONT_POWER_OPTIMIZE = "ON",
|
| 221 |
|
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 222 |
|
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MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 223 |
|
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OPERATION_MODE = "dual_port",
|
| 224 |
|
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PORT_A_ADDRESS_WIDTH = 5,
|
| 225 |
|
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PORT_A_DATA_WIDTH = 1,
|
| 226 |
|
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 227 |
|
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PORT_A_FIRST_ADDRESS = 0,
|
| 228 |
|
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PORT_A_FIRST_BIT_NUMBER = 6,
|
| 229 |
|
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PORT_A_LAST_ADDRESS = 31,
|
| 230 |
|
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PORT_A_LOGICAL_RAM_DEPTH = 32,
|
| 231 |
|
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PORT_A_LOGICAL_RAM_WIDTH = 8,
|
| 232 |
|
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PORT_B_ADDRESS_CLOCK = "clock0",
|
| 233 |
|
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PORT_B_ADDRESS_WIDTH = 5,
|
| 234 |
|
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PORT_B_DATA_OUT_CLEAR = "none",
|
| 235 |
|
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PORT_B_DATA_OUT_CLOCK = "none",
|
| 236 |
|
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PORT_B_DATA_WIDTH = 1,
|
| 237 |
|
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PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 238 |
|
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PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 239 |
|
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PORT_B_FIRST_ADDRESS = 0,
|
| 240 |
|
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PORT_B_FIRST_BIT_NUMBER = 6,
|
| 241 |
|
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PORT_B_LAST_ADDRESS = 31,
|
| 242 |
|
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PORT_B_LOGICAL_RAM_DEPTH = 32,
|
| 243 |
|
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PORT_B_LOGICAL_RAM_WIDTH = 8,
|
| 244 |
|
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PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 245 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 246 |
|
|
);
|
| 247 |
|
|
ram_block1a7 : stratixii_ram_block
|
| 248 |
|
|
WITH (
|
| 249 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 250 |
|
|
DONT_POWER_OPTIMIZE = "ON",
|
| 251 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 252 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 253 |
|
|
OPERATION_MODE = "dual_port",
|
| 254 |
|
|
PORT_A_ADDRESS_WIDTH = 5,
|
| 255 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 256 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 257 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 258 |
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
| 259 |
|
|
PORT_A_LAST_ADDRESS = 31,
|
| 260 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 32,
|
| 261 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
| 262 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 263 |
|
|
PORT_B_ADDRESS_WIDTH = 5,
|
| 264 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 265 |
|
|
PORT_B_DATA_OUT_CLOCK = "none",
|
| 266 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 267 |
|
|
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
| 268 |
|
|
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
| 269 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 270 |
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
| 271 |
|
|
PORT_B_LAST_ADDRESS = 31,
|
| 272 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 32,
|
| 273 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
| 274 |
|
|
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
|
| 275 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 276 |
|
|
);
|
| 277 |
|
|
address_a_wire[4..0] : WIRE;
|
| 278 |
|
|
address_b_wire[4..0] : WIRE;
|
| 279 |
|
|
|
| 280 |
|
|
BEGIN
|
| 281 |
|
|
ram_block1a[7..0].clk0 = clock0;
|
| 282 |
|
|
ram_block1a[7..0].portaaddr[] = ( address_a_wire[4..0]);
|
| 283 |
|
|
ram_block1a[0].portadatain[] = ( data_a[0..0]);
|
| 284 |
|
|
ram_block1a[1].portadatain[] = ( data_a[1..1]);
|
| 285 |
|
|
ram_block1a[2].portadatain[] = ( data_a[2..2]);
|
| 286 |
|
|
ram_block1a[3].portadatain[] = ( data_a[3..3]);
|
| 287 |
|
|
ram_block1a[4].portadatain[] = ( data_a[4..4]);
|
| 288 |
|
|
ram_block1a[5].portadatain[] = ( data_a[5..5]);
|
| 289 |
|
|
ram_block1a[6].portadatain[] = ( data_a[6..6]);
|
| 290 |
|
|
ram_block1a[7].portadatain[] = ( data_a[7..7]);
|
| 291 |
|
|
ram_block1a[7..0].portawe = wren_a;
|
| 292 |
|
|
ram_block1a[7..0].portbaddr[] = ( address_b_wire[4..0]);
|
| 293 |
|
|
ram_block1a[7..0].portbrewe = B"11111111";
|
| 294 |
|
|
address_a_wire[] = address_a[];
|
| 295 |
|
|
address_b_wire[] = address_b[];
|
| 296 |
|
|
q_b[] = ( ram_block1a[7..0].portbdataout[0..0]);
|
| 297 |
|
|
END;
|
| 298 |
|
|
--VALID FILE
|
