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vladimirar |
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Easier UVM Code Generator version 2016-04-18-EP (Send feedback to info@doulos.com)
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Parsing cmdline ...
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num args is 3
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Code generation will continue if critical warnings are issued
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pnum_c: 2
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Searching for regmodel flag
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Searching for prefix
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Searching for common template
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Searching for Syosil scoreboard path
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syosil_scoreboard_src_path: ../../playground_lib/uvm_syoscb/src
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pnum_s: 0
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Searching for templates
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T_List: rca.tpl
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List: rca.tpl
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Parsing common : common.tpl ...
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dut_top: rca
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top_default_seq_count = 8
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prefix for top-level names: top
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$regmodel = 0
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Parsing Templates ...
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Reading[1]: rca.tpl
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agent_name: agent_name = rca
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trans_item= trans
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trans_var: rand logic [15:0] input1;
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trans_var: rand logic [15:0] input2;
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trans_var: rand logic carryinput;
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trans_var: logic carryoutput;
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trans_var: logic [15:0] sum;
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trans_var: constraint c_addr_a { 0 <= input1; input1 < 5; }
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trans_var: constraint c_addr_b { 0 <= input2; input2 < 5; }
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if_port = logic [15:0] a;
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if_port = logic [15:0] b;
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if_port = logic ci;
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if_port = logic co;
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if_port = logic [15:0] s;
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if_port = logic clk;
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env_clock_list: rca clk
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clist[0]: rca
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clist[1]: clk
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driver_inc = rca_driver_inc.sv inline
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clist[0]: rca
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clist[1]: clk
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monitor_inc = rca_monitor_inc.sv inline
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clist[0]: rca
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clist[1]: clk
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dir: generated_tb/tb/rca
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Writing code to files
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AGENT-ITEM: trans
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var_decl=rand logic [15:0] input1;
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stripped_decl=rand logic input1;
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VARIABLE type = logic, var = input1
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var_decl=rand logic [15:0] input2;
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stripped_decl=rand logic input2;
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VARIABLE type = logic, var = input2
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var_decl=rand logic carryinput;
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stripped_decl=rand logic carryinput;
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VARIABLE type = logic, var = carryinput
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var_decl=logic carryoutput;
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stripped_decl=logic carryoutput;
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VARIABLE type = logic, var = carryoutput
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var_decl=logic [15:0] sum;
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stripped_decl=logic sum;
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VARIABLE type = logic, var = sum
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var_decl=constraint c_addr_a { 0 <= input1; input1 < 5; }
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Found constraint constraint c_addr_a { 0 <= input1; input1 < 5; }
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var_decl=constraint c_addr_b { 0 <= input2; input2 < 5; }
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Found constraint constraint c_addr_b { 0 <= input2; input2 < 5; }
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top env agents = rca
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Generating testbench in generated_tb/tb
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Writing ports for interface rca_if_0
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Generating simulator scripts in generated_tb/sim
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env_list=, agent_list=rca,
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env_list=, agent_list=rca,
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Code Generation complete
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