URL https://opencores.org/ocsvn/lxp32/lxp32/trunk

Subversion Repositories lxp32

[/] [lxp32/] [trunk/] [verify/] [icache/] [src/] [make/] [sources.make] - Blame information for rev 9

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# CPU RTL
 
LXP32_DIR=../../../../rtl
LXP32_RTL=$(LXP32_DIR)/lxp32_ram256x32.vhd\
        $(LXP32_DIR)/lxp32_icache.vhd
 
# Common package
 
COMMON_PKG_DIR=../../../common_pkg
COMMON_SRC=$(COMMON_PKG_DIR)/common_pkg.vhd $(COMMON_PKG_DIR)/common_pkg_body.vhd
 
# Testbench sources
 
TB_DIR=../../src/tb
TB_SRC=$(TB_DIR)/tb_pkg.vhd\
        $(TB_DIR)/cpu_model.vhd\
        $(TB_DIR)/ram_model.vhd\
        $(TB_DIR)/tb.vhd
 
TB_MOD=tb

Line No.	Rev	Author	Line
1	9	ring0_mipt	`# CPU RTL`
2
3			`LXP32_DIR=../../../../rtl`
4			`LXP32_RTL=$(LXP32_DIR)/lxp32_ram256x32.vhd\`
5			`$(LXP32_DIR)/lxp32_icache.vhd`
6
7			`# Common package`
8
9			`COMMON_PKG_DIR=../../../common_pkg`
10			`COMMON_SRC=$(COMMON_PKG_DIR)/common_pkg.vhd $(COMMON_PKG_DIR)/common_pkg_body.vhd`
11
12			`# Testbench sources`
13
14			`TB_DIR=../../src/tb`
15			`TB_SRC=$(TB_DIR)/tb_pkg.vhd\`
16			`$(TB_DIR)/cpu_model.vhd\`
17			`$(TB_DIR)/ram_model.vhd\`
18			`$(TB_DIR)/tb.vhd`
19
20			`TB_MOD=tb`

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Subversion Repositories lxp32

[/] [lxp32/] [trunk/] [verify/] [icache/] [src/] [make/] [sources.make] - Blame information for rev 9