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[/] [lxp32/] [trunk/] [verify/] [lxp32/] [src/] [platform/] [coprocessor.vhd] - Blame information for rev 12

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1 9 ring0_mipt
---------------------------------------------------------------------
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-- Coprocessor
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--
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-- Part of the LXP32 test platform
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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-- Performs a simple arithmetic operation, uses interrupt to wake
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-- up the CPU.
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--
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-- Note: regardless of whether this description is synthesizable,
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-- it was designed exclusively for simulation purposes.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity coprocessor is
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        port(
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                clk_i: in std_logic;
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                rst_i: in std_logic;
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                wbs_cyc_i: in std_logic;
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                wbs_stb_i: in std_logic;
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                wbs_we_i: in std_logic;
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                wbs_sel_i: in std_logic_vector(3 downto 0);
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                wbs_ack_o: out std_logic;
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                wbs_adr_i: in std_logic_vector(27 downto 2);
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                wbs_dat_i: in std_logic_vector(31 downto 0);
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                wbs_dat_o: out std_logic_vector(31 downto 0);
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                irq_o: out std_logic
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        );
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end entity;
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architecture rtl of coprocessor is
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signal value: unsigned(31 downto 0):=(others=>'0');
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signal result: unsigned(31 downto 0):=(others=>'0');
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signal cnt: integer range 0 to 50:=0;
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signal irq: std_logic:='0';
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begin
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process (clk_i) is
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begin
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        if rising_edge(clk_i) then
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                if rst_i='1' then
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                        value<=(others=>'0');
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                        cnt<=0;
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                        irq<='0';
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                else
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                        if cnt>0 then
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                                cnt<=cnt-1;
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                        end if;
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                        if cnt=1 then
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                                irq<='1';
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                        else
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                                irq<='0';
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                        end if;
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                        if wbs_cyc_i='1' and wbs_stb_i='1' and wbs_we_i='1' then
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                                for i in wbs_sel_i'range loop
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                                        if wbs_sel_i(i)='1' then
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                                                if wbs_adr_i="00"&X"000000" then
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                                                        value(i*8+7 downto i*8)<=
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                                                                unsigned(wbs_dat_i(i*8+7 downto i*8));
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                                                        cnt<=50;
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                                                end if;
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                                        end if;
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                                end loop;
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                        end if;
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                end if;
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        end if;
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end process;
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process (clk_i) is
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begin
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        if rising_edge(clk_i) then
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                if rst_i='1' then
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                        result<=(others=>'0');
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                else
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                        result<=shift_left(value,1)+value;
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                end if;
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        end if;
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end process;
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wbs_ack_o<=wbs_cyc_i and wbs_stb_i;
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wbs_dat_o<=std_logic_vector(value) when wbs_adr_i="00"&X"000000" else
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        std_logic_vector(result) when wbs_adr_i="00"&X"000001" else
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        (others=>'-');
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irq_o<=irq;
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end architecture;

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