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[/] [lxp32/] [trunk/] [verify/] [lxp32/] [src/] [platform/] [generic_dpram.vhd] - Blame information for rev 6

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1 2 ring0_mipt 
---------------------------------------------------------------------
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-- Generic FPGA memory block
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--
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-- Copyright (c) 2015 by Alex I. Kuznetsov
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--
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-- Portable description of a dual-port memory block with one write
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-- port.
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--
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-- Parameters:
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--     * DATA_WIDTH:  data port width
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--     * ADDR_WIDTH:  address port width
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--     * SIZE:        memory size
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--     * MODE:        read/write synchronization mode for port A
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--                      DONTCARE: choose the most efficient design
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--                      WR_FIRST: feed written value to the output
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--                      RD_FIRST: read old value
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--                      NOCHANGE: don't change output during write
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity generic_dpram is
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        generic(
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                DATA_WIDTH: integer;
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                ADDR_WIDTH: integer;
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                SIZE: integer;
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                MODE: string:="DONTCARE"
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        );
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        port(
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                clka_i: in std_logic;
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                cea_i: in std_logic;
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                wea_i: in std_logic;
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                addra_i: in std_logic_vector(ADDR_WIDTH-1 downto 0);
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                da_i: in std_logic_vector(DATA_WIDTH-1 downto 0);
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                da_o: out std_logic_vector(DATA_WIDTH-1 downto 0);
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                clkb_i: in std_logic;
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                ceb_i: in std_logic;
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                addrb_i: in std_logic_vector(ADDR_WIDTH-1 downto 0);
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                db_o: out std_logic_vector(DATA_WIDTH-1 downto 0)
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        );
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end entity;
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architecture rtl of generic_dpram is
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type ram_type is array(SIZE-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
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signal ram: ram_type;
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attribute syn_ramstyle: string;
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attribute syn_ramstyle of ram: signal is "no_rw_check";
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attribute ram_style: string; -- for Xilinx
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attribute ram_style of ram: signal is "block";
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begin
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-- Ensure that generics have valid values
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assert SIZE<=2**ADDR_WIDTH
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        report "SIZE must be less or equal than 2^ADDR_WIDTH"
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        severity failure;
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assert MODE="DONTCARE" or MODE="WR_FIRST" or MODE="RD_FIRST" or MODE="NOCHANGE"
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        report "Unrecognized MODE value (DONTCARE, WR_FIRST, RD_FIRST or NOCHANGE expected)"
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        severity failure;
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-- Port A (read/write)
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port_a_dont_care_gen: if MODE="DONTCARE" generate
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        process (clka_i) is
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        begin
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                if rising_edge(clka_i) then
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                        if cea_i='1' then
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                                if wea_i='1' then
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                                        ram(to_integer(unsigned(addra_i)))<=da_i;
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                                        da_o<=(others=>'-');
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                                else
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                                        if is_x(addra_i) then
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                                                da_o<=(others=>'X');
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                                        else
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                                                da_o<=ram(to_integer(unsigned(addra_i)));
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                                        end if;
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                                end if;
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                        end if;
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                end if;
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        end process;
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end generate;
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port_a_write_first_gen: if MODE="WR_FIRST" generate
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        process (clka_i) is
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        begin
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                if rising_edge(clka_i) then
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                        if cea_i='1' then
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                                if wea_i='1' then
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                                        ram(to_integer(unsigned(addra_i)))<=da_i;
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                                        da_o<=da_i;
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                                else
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                                        if is_x(addra_i) then
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                                                da_o<=(others=>'X');
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                                        else
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                                                da_o<=ram(to_integer(unsigned(addra_i)));
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                                        end if;
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                                end if;
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                        end if;
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                end if;
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        end process;
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end generate;
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port_a_read_first_gen: if MODE="RD_FIRST" generate
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        process (clka_i) is
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        begin
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                if rising_edge(clka_i) then
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                        if cea_i='1' then
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                                if wea_i='1' then
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                                        ram(to_integer(unsigned(addra_i)))<=da_i;
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                                end if;
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                                if is_x(addra_i) then
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                                        da_o<=(others=>'X');
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                                else
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                                        da_o<=ram(to_integer(unsigned(addra_i)));
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                                end if;
123 2 ring0_mipt 
                        end if;
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                end if;
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        end process;
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end generate;
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port_a_no_change_gen: if MODE="NOCHANGE" generate
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        process (clka_i) is
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        begin
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                if rising_edge(clka_i) then
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                        if cea_i='1' then
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                                if wea_i='1' then
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                                        ram(to_integer(unsigned(addra_i)))<=da_i;
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                                else
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                                        if is_x(addra_i) then
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                                                da_o<=(others=>'X');
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                                        else
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                                                da_o<=ram(to_integer(unsigned(addra_i)));
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                                        end if;
141 2 ring0_mipt 
                                end if;
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                        end if;
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                end if;
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        end process;
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end generate;
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-- Port B (read only)
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process (clkb_i) is
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begin
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        if rising_edge(clkb_i) then
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                if ceb_i='1' then
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                        if is_x(addrb_i) then
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                                db_o<=(others=>'X');
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                        else
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                                db_o<=ram(to_integer(unsigned(addrb_i)));
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                        end if;
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                end if;
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        end if;
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end process;
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end architecture;

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