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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright 2008-2013 by Michael A. Morris, dba M. A. Morris & Associates
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//
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// All rights reserved. The source code contained herein is publicly released
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// under the terms and conditions of the GNU Lesser Public License. No part of
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// this source code may be reproduced or transmitted in any form or by any
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// means, electronic or mechanical, including photocopying, recording, or any
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// information storage and retrieval system in violation of the license under
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// which the source code is released.
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//
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// The source code contained herein is free; it may be redistributed and/or
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// modified in accordance with the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either version 2.1 of
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// the GNU Lesser General Public License, or any later version.
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//
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// The source code contained herein is freely released WITHOUT ANY WARRANTY;
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// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
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// more details.)
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//
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// A copy of the GNU Lesser General Public License should have been received
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// along with the source code contained herein; if not, a copy can be obtained
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// by writing to:
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//
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// Free Software Foundation, Inc.
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// 51 Franklin Street, Fifth Floor
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// Boston, MA 02110-1301 USA
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//
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// Further, no use of this source code is permitted in any form or means
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// without inclusion of this banner prominently in any derived works.
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//
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// Michael A. Morris
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// Huntsville, AL
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//
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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///////////////////////////////////////////////////////////////////////////////
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// Company: M. A. Morris & Associates
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// Engineer: Michael A. Morris
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//
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// Create Date: 08:44:44 05/31/2008
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// Design Name: Synchronous Serial Peripheral (SSP) Interface UART
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// Module Name: ../VerilogCoponentsLib/SSP_UART/UART_RXSM.v
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// Project Name: Verilog Components Library
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// Target Devices: XC3S50A-4VQG100I, XC3S20A-4VQG100I, XC3S700AN-4FFG484I
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// Tool versions: ISE 10.1i SP3
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//
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// Description: This module implements the SSP UART Receive State Machine
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//
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// Dependencies: None
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//
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// Revision History:
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//
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// 0.01 08E31 MAM File Created
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//
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// 1.00 08F08 MAM Module Released
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//
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// 1.01 08F12 MAM Pulled Format Decoder ROM and added its outputs to
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// the port list. Allows greater format specification
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// flexibility. 7-bit formats require parity. If ParEn
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// is not set, the parity will be tested according to
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// the settings of the Par bits, which may result in
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// anomalous behavior.
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//
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// 2.00 11B06 MAM Converted to Verilog 2001.
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//
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// Additional Comments:
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//
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///////////////////////////////////////////////////////////////////////////////
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module UART_RXSM(
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input Rst,
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input Clk,
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input CE_16x, // 16x Clock Enable - Baud Rate x16
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input Len, // Word length: 0 - 8-bits; 1 - 7 bits
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input NumStop, // Number Stop Bits: 0 - 1 Stop; 1 - 2 Stop
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input ParEn, // Parity Enable
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input [1:0] Par, // 0 - Odd; 1 - Even; 2 - Space (0); 3 - Mark (1)
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input RxD, // Input Asynchronous Serial Receive Data
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output reg [8:0] RD, // Receive Data Output - bit 8 = Rcv Error (RERR)
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output reg WE_RHR, // Write Enable - Receive Holding Register
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output RxWait, // RxSM - Wait State
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output RxIdle, // RxSM - Idle State
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output RxStart, // RxSM - Start Bit Check State
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output RxShift, // RxSM - RxD Shift State
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output RxParity, // RxSM - RxD Parity Shift State
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output RxStop, // RxSM - RxD Stop Bit Check States
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output RxError // RxSM - Error State
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);
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///////////////////////////////////////////////////////////////////////////////
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//
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// Module Parameters
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//
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// Receive State Machine Declarations (Binary)
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localparam pWaitMark = 0;
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localparam pChkMark = 1;
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localparam pIdle = 3;
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localparam pChkStart = 2;
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localparam pShift0 = 10;
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localparam pShift1 = 11;
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localparam pShift2 = 9;
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localparam pShift3 = 8;
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localparam pShift4 = 12;
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localparam pShift5 = 13;
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localparam pShift6 = 15;
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localparam pShift7 = 14;
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localparam pChkStop1 = 6;
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localparam pChkStop2 = 7;
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localparam pChkParity = 5;
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localparam pRcvError = 4;
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///////////////////////////////////////////////////////////////////////////////
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//
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// Local Signal Declarations
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//
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(* FSM_ENCODING="SEQUENTIAL",
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SAFE_IMPLEMENTATION="YES",
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SAFE_RECOVERY_STATE="4'b0" *) reg [3:0] RxSM = pWaitMark;
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reg [3:0] BCnt;
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reg [7:0] RSR;
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reg Err;
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///////////////////////////////////////////////////////////////////////////////
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//
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// Implementation
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// RxSM Decode
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//
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assign RxSM_Wait = ( (RxSM == pWaitMark)
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| (RxSM == pChkMark)
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| (RxSM == pIdle)
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| (RxSM == pRcvError) );
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assign RxWait = RxSM_Wait;
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assign RxIdle = (RxSM == pIdle);
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assign RxStart = (RxSM == pChkStart);
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assign RxShift = ( (RxSM == pShift0)
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| (RxSM == pShift1)
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| (RxSM == pShift2)
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| (RxSM == pShift3)
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| (RxSM == pShift4)
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| (RxSM == pShift5)
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| (RxSM == pShift6)
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| (RxSM == pShift7) );
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assign RxParity = (RxSM == pChkParity);
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assign RxStop = (RxSM == pChkStop1) | (RxSM == pChkStop2);
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assign RxError = (RxSM == pRcvError);
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///////////////////////////////////////////////////////////////////////////////
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//
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// Bit Rate Prescaler
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//
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// Prescaler is held in the half-bit load state during reset and when the
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// RXSM is in the RxSM_Wait states. As a consequence, the first overflow
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// is only half a bit period, and only occurs in the pChkStart state.
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// Subsequent, overflows are occur once per bit period in the middle of
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// each of the remaining bits.
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//
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assign Rst_BCnt = Rst | RxSM_Wait;
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always @(posedge Clk)
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begin
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if(Rst_BCnt)
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BCnt <= #1 4'b1000;
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else if(CE_16x)
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BCnt <= #1 BCnt + 1;
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end
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assign TC_BCnt = CE_16x & (BCnt == 4'b1111);
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///////////////////////////////////////////////////////////////////////////////
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assign CE_RxSM = (RxSM_Wait ? CE_16x : TC_BCnt);
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///////////////////////////////////////////////////////////////////////////////
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//
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// Receive Shift Register
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//
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always @(posedge Clk)
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begin
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if(Rst)
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RSR <= #1 8'b0;
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else if(CE_RxSM)
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case(RxSM)
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pChkStart : RSR <= #1 8'b0;
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pShift0 : RSR[0] <= #1 RxD;
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pShift1 : RSR[1] <= #1 RxD;
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pShift2 : RSR[2] <= #1 RxD;
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pShift3 : RSR[3] <= #1 RxD;
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pShift4 : RSR[4] <= #1 RxD;
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pShift5 : RSR[5] <= #1 RxD;
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pShift6 : RSR[6] <= #1 RxD;
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pShift7 : RSR[7] <= #1 RxD;
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default : RSR <= #1 RSR;
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endcase
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end
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///////////////////////////////////////////////////////////////////////////////
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//
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// Parity Checker
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// if not Check Parity State, then ParErr = 0
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//
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assign OddPar = ^{RxD, RSR};
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assign EvnPar = ~OddPar;
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always @(*)
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begin
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case(Par)
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2'b00 : Err <= ~OddPar;
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2'b01 : Err <= ~EvnPar;
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2'b10 : Err <= RxD;
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2'b11 : Err <= ~RxD;
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endcase
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end
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assign ParErr = Err & (RxSM == pChkParity);
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///////////////////////////////////////////////////////////////////////////////
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//
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// Receive Holding Register Data
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//
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assign CE_RD = CE_RxSM & (((RxSM == pChkStop1) & RxD) | (RxSM == pRcvError));
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always @(posedge Clk)
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begin
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if(Rst)
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RD <= #1 9'b0;
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else if(CE_RD)
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RD <= #1 {(RxSM == pRcvError), RSR};
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end
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always @(posedge Clk)
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begin
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if(Rst)
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WE_RHR <= #1 1'b0;
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else
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WE_RHR <= #1 CE_RD;
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end
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///////////////////////////////////////////////////////////////////////////////
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//
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// RxSM - Receive State Machine
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//
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// The Receive State Machine starts in the WaitMark state to insure that
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// the receive line is in the marking state before continuing. The ChkMark
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// state validates that the receive line is in the marking state. If it
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// is, then the RxSM is adanced to the Idle state to wait for the start
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// bit. Otherwise, RxSM returns to the WaitMark state to wait for the line
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// to return to the marking (idle) state.
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//
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// The format is processed through the receive sequence. The length,
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// parity options, and the number of stop bits determine the state tran-
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// sitions that the RxSM makes. A parity or a framing error is simply
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// recorded as an error with the 9th bit of the receive holding register.
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// Line break conditions, invalid stop bits, etc. are handled through the
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// pRcvError and the pWaitMark states. Thus, line break conditions are not
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// expected to cause the RxSM to receive more than one character, and the
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// pWaitMark state holds the receiver in a wait state until the line
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// returns to the marking (idle) state.
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//
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always @(posedge Clk)
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begin
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if(Rst)
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RxSM <= #1 pWaitMark;
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else if(CE_RxSM)
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case(RxSM)
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pWaitMark : RxSM <= #1 ( RxD ? pChkMark
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: pWaitMark);
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pChkMark : RxSM <= #1 ( RxD ? pIdle
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: pWaitMark);
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pIdle : RxSM <= #1 (~RxD ? pChkStart
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: pIdle);
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pChkStart : RxSM <= #1 ( RxD ? pIdle
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: pShift0);
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pShift0 : RxSM <= #1 pShift1;
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pShift1 : RxSM <= #1 pShift2;
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pShift2 : RxSM <= #1 pShift3;
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pShift3 : RxSM <= #1 pShift4;
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pShift4 : RxSM <= #1 pShift5;
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pShift5 : RxSM <= #1 pShift6;
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pShift6 : RxSM <= #1 (Len ? pChkParity
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: pShift7);
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pShift7 : RxSM <= #1 (ParEn ? pChkParity
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: (NumStop ? pChkStop2
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: pChkStop1));
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pChkParity : RxSM <= #1 (ParErr ? pRcvError
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: (NumStop ? pChkStop2
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: pChkStop1));
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pChkStop2 : RxSM <= #1 (RxD ? pChkStop1
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: pRcvError);
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pChkStop1 : RxSM <= #1 (RxD ? pIdle
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: pRcvError);
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pRcvError : RxSM <= #1 pWaitMark;
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default : RxSM <= #1 pWaitMark;
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endcase
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end
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endmodule
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