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[/] [m65c02/] [trunk/] [Src/] [RTL/] [M65C02.tcl] - Blame information for rev 2

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Line No. Rev Author Line
1 2 MichaelA
# 
2
# Project automation script for M65C02 
3
# 
4
# Created for ISE version 10.1
5
# 
6
# This file contains several Tcl procedures (procs) that you can use to automate
7
# your project by running from xtclsh or the Project Navigator Tcl console.
8
# If you load this file (using the Tcl command: source C:/XProjects/ISE10.1i/M65C02/Src/M65C02.tcl, then you can
9
# run any of the procs included here.
10
# You may also edit any of these procs to customize them. See comments in each
11
# proc for more instructions.
12
# 
13
# This file contains the following procedures:
14
# 
15
# Top Level procs (meant to be called directly by the user):
16
#    run_process: you can use this top-level procedure to run any processes
17
#        that you choose to by adding and removing comments, or by
18
#        adding new entries.
19
#    rebuild_project: you can alternatively use this top-level procedure
20
#        to recreate your entire project, and the run selected processes.
21
# 
22
# Lower Level (helper) procs (called under in various cases by the top level procs):
23
#    show_help: print some basic information describing how this script works
24
#    add_source_files: adds the listed source files to your project.
25
#    set_project_props: sets the project properties that were in effect when this
26
#        script was generated.
27
#    create_libraries: creates and adds file to VHDL libraries that were defined when
28
#        this script was generated.
29
#    create_partitions: adds any partitions that were defined when this script was generated.
30
#    set_process_props: set the process properties as they were set for your project
31
#        when this script was generated.
32
# 
33
 
34
set myProject "M65C02.ise"
35
set myScript "C:/XProjects/ISE10.1i/M65C02/Src/M65C02.tcl"
36
 
37
# 
38
# Main (top-level) routines
39
# 
40
 
41
# 
42
# run_process
43
# This procedure is used to run processes on an existing project. You may comment or
44
# uncomment lines to control which processes are run. This routine is set up to run
45
# the Implement Design and Generate Programming File processes by default. This proc
46
# also sets process properties as specified in the "set_process_props" proc. Only
47
# those properties which have values different from their current settings in the project
48
# file will be modified in the project.
49
# 
50
proc run_process {} {
51
 
52
   global myScript
53
   global myProject
54
 
55
   ## put out a 'heartbeat' - so we know something's happening.
56
   puts "\n$myScript: running ($myProject)...\n"
57
 
58
   if { ! [ open_project ] } {
59
      return false
60
   }
61
 
62
   set_process_props
63
   #
64
   # Remove the comment characters (#'s) to enable the following commands 
65
   # process run "Synthesize"
66
   # process run "Translate"
67
   # process run "Map"
68
   # process run "Place & Route"
69
   #
70
   puts "Running 'Implement Design'"
71
   if { ! [ process run "Implement Design" ] } {
72
      puts "$myScript: Implementation run failed, check run output for details."
73
      project close
74
      return
75
   }
76
   puts "Running 'Generate Programming File'"
77
   if { ! [ process run "Generate Programming File" ] } {
78
      puts "$myScript: Generate Programming File run failed, check run output for details."
79
      project close
80
      return
81
   }
82
 
83
   puts "Run completed."
84
   project close
85
 
86
}
87
 
88
# 
89
# rebuild_project
90
# 
91
# This procedure renames the project file (if it exists) and recreates the project.
92
# It then sets project properties and adds project sources as specified by the
93
# set_project_props and add_source_files support procs. It recreates VHDL libraries
94
# and partitions as they existed at the time this script was generated.
95
# 
96
# It then calls run_process to set process properties and run selected processes.
97
# 
98
proc rebuild_project {} {
99
 
100
   global myScript
101
   global myProject
102
 
103
   ## put out a 'heartbeat' - so we know something's happening.
104
   puts "\n$myScript: rebuilding ($myProject)...\n"
105
 
106
   if { [ file exists $myProject ] } {
107
      puts "$myScript: Removing existing project file."
108
      file delete $myProject
109
   }
110
 
111
   puts "$myScript: Rebuilding project $myProject"
112
   project new $myProject
113
   set_project_props
114
   add_source_files
115
   create_libraries
116
   create_partitions
117
   puts "$myScript: project rebuild completed."
118
 
119
   run_process
120
 
121
}
122
 
123
# 
124
# Support Routines
125
# 
126
 
127
# 
128
# show_help: print information to help users understand the options available when
129
#            running this script.
130
# 
131
proc show_help {} {
132
 
133
   global myScript
134
 
135
   puts ""
136
   puts "usage: xtclsh $myScript <options>"
137
   puts "       or you can run xtclsh and then enter 'source $myScript'."
138
   puts ""
139
   puts "options:"
140
   puts "   run_process       - set properties and run processes."
141
   puts "   rebuild_project   - rebuild the project from scratch and run processes."
142
   puts "   set_project_props - set project properties (device, speed, etc.)"
143
   puts "   add_source_files  - add source files"
144
   puts "   create_libraries  - create vhdl libraries"
145
   puts "   create_partitions - create partitions"
146
   puts "   set_process_props - set process property values"
147
   puts "   show_help         - print this message"
148
   puts ""
149
}
150
 
151
proc open_project {} {
152
 
153
   global myScript
154
   global myProject
155
 
156
   if { ! [ file exists $myProject ] } {
157
      ## project file isn't there, rebuild it.
158
      puts "Project $myProject not found. Use project_rebuild to recreate it."
159
      return false
160
   }
161
 
162
   project open $myProject
163
 
164
   return true
165
 
166
}
167
# 
168
# set_project_props
169
# 
170
# This procedure sets the project properties as they were set in the project
171
# at the time this script was generated.
172
# 
173
proc set_project_props {} {
174
 
175
   global myScript
176
 
177
   if { ! [ open_project ] } {
178
      return false
179
   }
180
 
181
   puts "$myScript: Setting project properties..."
182
 
183
   project set family "Spartan3A and Spartan3AN"
184
   project set device "xc3s50a"
185
   project set package "vq100"
186
   project set speed "-4"
187
   project set top_level_module_type "HDL"
188
   project set synthesis_tool "XST (VHDL/Verilog)"
189
   project set simulator "ISE Simulator (VHDL/Verilog)"
190
   project set "Preferred Language" "Verilog"
191
   project set "Enable Message Filtering" "true"
192
   project set "Display Incremental Messages" "true"
193
 
194
}
195
 
196
 
197
# 
198
# add_source_files
199
# 
200
# This procedure add the source files that were known to the project at the
201
# time this script was generated.
202
# 
203
proc add_source_files {} {
204
 
205
   global myScript
206
 
207
   if { ! [ open_project ] } {
208
      return false
209
   }
210
 
211
   puts "$myScript: Adding sources to project..."
212
 
213
   xfile add "ClkGen.xaw"
214
   xfile add "Src/M65C02.ucf"
215
   xfile add "Src/M65C02.v"
216
   xfile add "Src/M65C02_ALU.v"
217
   xfile add "Src/M65C02_AddrGen.v"
218
   xfile add "Src/M65C02_BCD.v"
219
   xfile add "Src/M65C02_BIN.v"
220
   xfile add "Src/M65C02_Base.v"
221
   xfile add "Src/M65C02_BrdTst.ucf"
222
   xfile add "Src/M65C02_BrdTst.v"
223
   xfile add "Src/M65C02_Core.v"
224
   xfile add "Src/M65C02_MPC.v"
225
   xfile add "Src/M65C02_MPCv3.v"
226
   xfile add "Src/M65C02_MPCv4.v"
227
   xfile add "Src/M65C02_RAM.v"
228
   xfile add "Src/fedet.v"
229
   xfile add "Src/tb_M65C02.v"
230
   xfile add "Src/tb_M65C02_ALU.v"
231
   xfile add "Src/tb_M65C02_AddrGen.v"
232
   xfile add "Src/tb_M65C02_BCD.v"
233
   xfile add "Src/tb_M65C02_Core.v"
234
   xfile add "Src/tb_M65C02_RAM.v"
235
 
236
   # Set the Top Module as well...
237
   project set top "M65C02"
238
 
239
   puts "$myScript: project sources reloaded."
240
 
241
} ; # end add_source_files
242
 
243
# 
244
# create_libraries
245
# 
246
# This procedure defines VHDL libraries and associates files with those libraries.
247
# It is expected to be used when recreating the project. Any libraries defined
248
# when this script was generated are recreated by this procedure.
249
# 
250
proc create_libraries {} {
251
 
252
   global myScript
253
 
254
   if { ! [ open_project ] } {
255
      return false
256
   }
257
 
258
   puts "$myScript: Creating libraries..."
259
   # note: if you have multiple files with the same name at different paths,
260
   # you may have problems with the lib_vhdl command.
261
 
262
 
263
   # must close the project or library definitions aren't saved, then reopen it for further use.
264
   project close
265
   open_project
266
 
267
} ; # end create_libraries
268
 
269
#
270
# create_partitions
271
#
272
# This procedure creates partitions on instances in your project.
273
# It is expected to be used when recreating the project. Any partitions
274
# defined when this script was generated are recreated by this procedure.
275
# 
276
proc create_partitions {} {
277
 
278
   global myScript
279
 
280
   if { ! [ open_project ] } {
281
      return false
282
   }
283
 
284
   puts "$myScript: Creating Partitions..."
285
 
286
 
287
   # must close the project or partition definitions aren't saved, then reopen it for further use.
288
   project close
289
   open_project
290
 
291
} ; # end create_partitions
292
 
293
# 
294
# set_process_props
295
# 
296
# This procedure sets properties as requested during script generation (either
297
# all of the properties, or only those modified from their defaults).
298
# 
299
proc set_process_props {} {
300
 
301
   global myScript
302
 
303
   if { ! [ open_project ] } {
304
      return false
305
   }
306
 
307
   puts "$myScript: setting process properties..."
308
 
309
   project set "Compiled Library Directory" "\$XILINX/<language>/<simulator>"
310
   project set "Use SmartGuide" "false"
311
   project set "SmartGuide Filename" "M65C02_guide.ncd"
312
   project set "Multiplier Style" "Auto" -process "Synthesize - XST"
313
   project set "Configuration Rate" "25" -process "Generate Programming File"
314
   project set "Map to Input Functions" "4" -process "Map"
315
   project set "Number of Clock Buffers" "24" -process "Synthesize - XST"
316
   project set "Max Fanout" "500" -process "Synthesize - XST"
317
   project set "Case Implementation Style" "None" -process "Synthesize - XST"
318
   project set "Decoder Extraction" "true" -process "Synthesize - XST"
319
   project set "Priority Encoder Extraction" "Yes" -process "Synthesize - XST"
320
   project set "Mux Extraction" "Yes" -process "Synthesize - XST"
321
   project set "RAM Extraction" "true" -process "Synthesize - XST"
322
   project set "ROM Extraction" "true" -process "Synthesize - XST"
323
   project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
324
   project set "Logical Shifter Extraction" "true" -process "Synthesize - XST"
325
   project set "Optimization Goal" "Area" -process "Synthesize - XST"
326
   project set "Optimization Effort" "High" -process "Synthesize - XST"
327
   project set "Resource Sharing" "true" -process "Synthesize - XST"
328
   project set "Shift Register Extraction" "true" -process "Synthesize - XST"
329
   project set "XOR Collapsing" "true" -process "Synthesize - XST"
330
   project set "Other Bitgen Command Line Options" "" -process "Generate Programming File"
331
   project set "Show All Models" "false" -process "Generate IBIS Model"
332
   project set "Target UCF File Name" "" -process "Back-annotate Pin Locations"
333
   project set "Ignore User Timing Constraints" "false" -process "Map"
334
   project set "Use RLOC Constraints" "true" -process "Map"
335
   project set "Other Map Command Line Options" "" -process "Map"
336
   project set "Use LOC Constraints" "true" -process "Translate"
337
   project set "Other Ngdbuild Command Line Options" "" -process "Translate"
338
   project set "Ignore User Timing Constraints" "false" -process "Place & Route"
339
   project set "Other Place & Route Command Line Options" "" -process "Place & Route"
340
   project set "UserID Code (8 Digit Hexadecimal)" "0x4D414D00" -process "Generate Programming File"
341
   project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
342
   project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
343
   project set "Create Binary Configuration File" "false" -process "Generate Programming File"
344
   project set "Create Bit File" "true" -process "Generate Programming File"
345
   project set "Enable BitStream Compression" "false" -process "Generate Programming File"
346
   project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
347
   project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
348
   project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File"
349
   project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
350
   project set "Place MultiBoot Settings into Bitstream" "false" -process "Generate Programming File"
351
   project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
352
   project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
353
   project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
354
   project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
355
   project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
356
   project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
357
   project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
358
   project set "Done (Output Events)" "6" -process "Generate Programming File"
359
   project set "Drive Done Pin High" "false" -process "Generate Programming File"
360
   project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
361
   project set "Release DLL (Output Events)" "Default (NoWait)" -process "Generate Programming File"
362
   project set "Release Write Enable (Output Events)" "4" -process "Generate Programming File"
363
   project set "Enable Internal Done Pipe" "false" -process "Generate Programming File"
364
   project set "Drive Awake Pin During Suspend/Wake Sequence" "false" -process "Generate Programming File"
365
   project set "Enable Filter on Suspend Input" "true" -process "Generate Programming File"
366
   project set "Enable Suspend/Wake Global Set/Reset" "false" -process "Generate Programming File"
367
   project set "Enable Power-On Reset Detection" "true" -process "Generate Programming File"
368
   project set "GTS Cycle During Suspend/Wakeup Sequence" "4" -process "Generate Programming File"
369
   project set "GWE Cycle During Suspend/Wakeup Sequence" "5" -process "Generate Programming File"
370
   project set "Wakeup Clock" "Startup Clock" -process "Generate Programming File"
371
   project set "Allow Logic Optimization Across Hierarchy" "true" -process "Map"
372
   project set "Optimization Strategy (Cover Mode)" "Area" -process "Map"
373
   project set "Disable Register Ordering" "true" -process "Map"
374
   project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" -process "Map"
375
   project set "Replicate Logic to Allow Logic Level Reduction" "true" -process "Map"
376
   project set "Generate Detailed MAP Report" "true" -process "Map"
377
   project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map"
378
   project set "Perform Timing-Driven Packing and Placement" "true" -process "Map"
379
   project set "Trim Unconnected Signals" "true" -process "Map"
380
   project set "Create I/O Pads from Ports" "false" -process "Translate"
381
   project set "Macro Search Path" "" -process "Translate"
382
   project set "Netlist Translation Type" "Timestamp" -process "Translate"
383
   project set "User Rules File for Netlister Launcher" "" -process "Translate"
384
   project set "Allow Unexpanded Blocks" "false" -process "Translate"
385
   project set "Allow Unmatched LOC Constraints" "false" -process "Translate"
386
   project set "Starting Placer Cost Table (1-100)" "5" -process "Place & Route"
387
   project set "Placer Effort Level (Overrides Overall Level)" "High" -process "Place & Route"
388
   project set "Router Effort Level (Overrides Overall Level)" "High" -process "Place & Route"
389
   project set "Place And Route Mode" "Multi Pass Place and Route" -process "Place & Route"
390
   project set "Use Bonded I/Os" "false" -process "Place & Route"
391
   project set "Add I/O Buffers" "true" -process "Synthesize - XST"
392
   project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
393
   project set "Keep Hierarchy" "No" -process "Synthesize - XST"
394
   project set "Register Balancing" "Yes" -process "Synthesize - XST"
395
   project set "Register Duplication" "true" -process "Synthesize - XST"
396
   project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
397
   project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
398
   project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
399
   project set "Bus Delimiter" "<>" -process "Synthesize - XST"
400
   project set "Case" "Maintain" -process "Synthesize - XST"
401
   project set "Cores Search Directories" "" -process "Synthesize - XST"
402
   project set "Cross Clock Analysis" "true" -process "Synthesize - XST"
403
   project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
404
   project set "FSM Style" "LUT" -process "Synthesize - XST"
405
   project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
406
   project set "Generics, Parameters" "" -process "Synthesize - XST"
407
   project set "Hierarchy Separator" "/" -process "Synthesize - XST"
408
   project set "HDL INI File" "" -process "Synthesize - XST"
409
   project set "Library Search Order" "" -process "Synthesize - XST"
410
   project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
411
   project set "Optimize Instantiated Primitives" "true" -process "Synthesize - XST"
412
   project set "Pack I/O Registers into IOBs" "Yes" -process "Synthesize - XST"
413
   project set "Read Cores" "true" -process "Synthesize - XST"
414
   project set "Slice Packing" "true" -process "Synthesize - XST"
415
   project set "Slice Utilization Ratio" "100" -process "Synthesize - XST"
416
   project set "Use Clock Enable" "Yes" -process "Synthesize - XST"
417
   project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST"
418
   project set "Use Synchronous Set" "Yes" -process "Synthesize - XST"
419
   project set "Use Synthesis Constraints File" "false" -process "Synthesize - XST"
420
   project set "Custom Compile File List" "" -process "Synthesize - XST"
421
   project set "Verilog Include Directories" "" -process "Synthesize - XST"
422
   project set "Verilog 2001" "true" -process "Synthesize - XST"
423
   project set "Verilog Macros" "" -process "Synthesize - XST"
424
   project set "Work Directory" "./xst" -process "Synthesize - XST"
425
   project set "Write Timing Constraints" "true" -process "Synthesize - XST"
426
   project set "Other XST Command Line Options" "" -process "Synthesize - XST"
427
   project set "Map Effort Level" "High" -process "Map"
428
   project set "Combinatorial Logic Optimization" "true" -process "Map"
429
   project set "Starting Placer Cost Table (1-100)" "5" -process "Map"
430
   project set "Power Reduction" "false" -process "Map"
431
   project set "Register Duplication" "true" -process "Map"
432
   project set "Synthesis Constraints File" "" -process "Synthesize - XST"
433
   project set "Mux Style" "Auto" -process "Synthesize - XST"
434
   project set "RAM Style" "Auto" -process "Synthesize - XST"
435
   project set "Timing Mode" "Non Timing Driven" -process "Map"
436
   project set "Generate Asynchronous Delay Report" "true" -process "Place & Route"
437
   project set "Generate Clock Region Report" "false" -process "Place & Route"
438
   project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
439
   project set "Generate Post-Place & Route Static Timing Report" "false" -process "Place & Route"
440
   project set "Nodelist File (Unix Only)" "" -process "Place & Route"
441
   project set "Number of PAR Iterations (0-100)" "3" -process "Place & Route"
442
   project set "Save Results in Directory (.dir will be appended)" "mppr_result" -process "Place & Route"
443
   project set "Number of Results to Save (0-100)" "" -process "Place & Route"
444
   project set "Power Reduction" "false" -process "Place & Route"
445
   project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
446
   project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
447
   project set "Retry Configuration if CRC Error Occurs" "false" -process "Generate Programming File"
448
   project set "MultiBoot: Starting Address for Next Configuration" "0x00000000" -process "Generate Programming File"
449
   project set "MultiBoot: Use New Mode for Next Configuration" "false" -process "Generate Programming File"
450
   project set "CLB Pack Factor Percentage" "100" -process "Map"
451
   project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route"
452
   project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
453
   project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST"
454
   project set "ROM Style" "Auto" -process "Synthesize - XST"
455
   project set "Safe Implementation" "No" -process "Synthesize - XST"
456
   project set "Extra Effort" "Continue on Impossible" -process "Map"
457
   project set "Power Activity File" "" -process "Map"
458
   project set "Power Activity File" "" -process "Place & Route"
459
   project set "MultiBoot: Next Configuration Mode" "000" -process "Generate Programming File"
460
   project set "Extra Effort (Highest PAR level only)" "Continue on Impossible" -process "Place & Route"
461
 
462
   puts "$myScript: project property values set."
463
 
464
} ; # end set_process_props
465
 
466
proc main {} {
467
 
468
   if { [llength $::argv] == 0 } {
469
      show_help
470
      return true
471
   }
472
 
473
   foreach option $::argv {
474
      switch $option {
475
         "show_help"           { show_help }
476
         "run_process"         { run_process }
477
         "rebuild_project"     { rebuild_project }
478
         "set_project_props"   { set_project_props }
479
         "add_source_files"    { add_source_files }
480
         "create_libraries"    { create_libraries }
481
         "create_partitions"   { create_partitions }
482
         "set_process_props"   { set_process_props }
483
         default               { puts "unrecognized option: $option"; show_help }
484
      }
485
   }
486
}
487
 
488
if { $tcl_interactive } {
489
   show_help
490
} else {
491
   if {[catch {main} result]} {
492
      puts "$myScript failed: $result."
493
   }
494
}
495
 

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