1 |
2 |
skeptonomi |
--*************************************************************************
|
2 |
|
|
--* *
|
3 |
|
|
--* Copyright (C) 2014 William B Hunter - LGPL *
|
4 |
|
|
--* *
|
5 |
|
|
--* This source file may be used and distributed without *
|
6 |
|
|
--* restriction provided that this copyright statement is not *
|
7 |
|
|
--* removed from the file and that any derivative work contains *
|
8 |
|
|
--* the original copyright notice and the associated disclaimer. *
|
9 |
|
|
--* *
|
10 |
|
|
--* This source file is free software; you can redistribute it *
|
11 |
|
|
--* and/or modify it under the terms of the GNU Lesser General *
|
12 |
|
|
--* Public License as published by the Free Software Foundation; *
|
13 |
|
|
--* either version 2.1 of the License, or (at your option) any *
|
14 |
|
|
--* later version. *
|
15 |
|
|
--* *
|
16 |
|
|
--* This source is distributed in the hope that it will be *
|
17 |
|
|
--* useful, but WITHout ANY WARRANTY; without even the implied *
|
18 |
|
|
--* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR *
|
19 |
|
|
--* PURPOSE. See the GNU Lesser General Public License for more *
|
20 |
|
|
--* details. *
|
21 |
|
|
--* *
|
22 |
|
|
--* You should have received a copy of the GNU Lesser General *
|
23 |
|
|
--* Public License along with this source; if not, download it *
|
24 |
|
|
--* from http://www.opencores.org/lgpl.shtml *
|
25 |
|
|
--* *
|
26 |
|
|
--*************************************************************************
|
27 |
|
|
--
|
28 |
|
|
-- Engineer: William B Hunter
|
29 |
|
|
-- Create Date: 08/08/2014
|
30 |
|
|
-- Project: Manchester Uart
|
31 |
|
|
-- File: encode.vhd
|
32 |
|
|
-- Description: This encoder sends out short bursts of 16 bit data words encoded with as manchester data.
|
33 |
|
|
-- Because this is not a stream encoder, it has no sync pattern or packet alignment typical of manchester encoders.
|
34 |
|
|
-- It therefor uses start and stop bits much like a UART. Both the start and stop bits are always ones. The idle
|
35 |
|
|
-- state is always high, and the ones are a low to high transition in the middle of the bit period, and a zero is a
|
36 |
|
|
-- high to low transition in the middle of the bit period. A high for 3 bit periods is a reset/resync.
|
37 |
|
|
----------------------------------------------------------------------------------
|
38 |
|
|
|
39 |
|
|
|
40 |
|
|
library IEEE;
|
41 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
42 |
|
|
use IEEE.NUMERIC_STD.ALL;
|
43 |
|
|
|
44 |
|
|
entity encode is
|
45 |
|
|
Port (
|
46 |
|
|
clk16x : in STD_LOGIC;
|
47 |
|
|
srst : in STD_LOGIC;
|
48 |
|
|
tx_data : in STD_LOGIC_VECTOR (15 downto 0);
|
49 |
|
|
tx_stb : in STD_LOGIC;
|
50 |
|
|
txd : out STD_LOGIC;
|
51 |
|
|
or_err : out STD_LOGIC;
|
52 |
|
|
tx_idle : out STD_LOGIC
|
53 |
|
|
);
|
54 |
|
|
end encode;
|
55 |
|
|
|
56 |
|
|
architecture rtl of encode is
|
57 |
|
|
signal shifter : std_logic_vector(15 downto 0);
|
58 |
|
|
signal tick_cnt : integer range 0 to 15 := 0;
|
59 |
|
|
signal bit_cnt : integer range 0 to 15 := 0;
|
60 |
|
|
signal txd_int : std_logic := '1';
|
61 |
|
|
signal err_int : std_logic := '0';
|
62 |
|
|
|
63 |
|
|
type txr_state_type is (SM_IDLE, SM_START, SM_SEND, SM_STOP);
|
64 |
|
|
signal txr_state : txr_state_type := SM_IDLE;
|
65 |
|
|
|
66 |
|
|
begin
|
67 |
|
|
|
68 |
|
|
p_transmitter: process(clk16x)
|
69 |
|
|
begin
|
70 |
|
|
if rising_edge(clk16x) then
|
71 |
|
|
if srst = '1' then
|
72 |
|
|
txr_state <= SM_IDLE;
|
73 |
|
|
tick_cnt <= 0;
|
74 |
|
|
bit_cnt <= 0;
|
75 |
|
|
else
|
76 |
|
|
case txr_state is
|
77 |
|
|
--wait for a tx strobe to start a transmission
|
78 |
|
|
when SM_IDLE =>
|
79 |
|
|
tick_cnt <= 0;
|
80 |
|
|
bit_cnt <= 0;
|
81 |
|
|
if tx_stb = '1' then
|
82 |
|
|
txr_state <= SM_START;
|
83 |
|
|
shifter <= tx_data;
|
84 |
|
|
end if;
|
85 |
|
|
--the start is a one, which is 8 ticks low followed by 8 ticks high
|
86 |
|
|
when SM_START =>
|
87 |
|
|
if tick_cnt < 8 then
|
88 |
|
|
txd_int <= '0';
|
89 |
|
|
tick_cnt <= tick_cnt + 1;
|
90 |
|
|
elsif tick_cnt < 15 then
|
91 |
|
|
txd_int <= '1';
|
92 |
|
|
tick_cnt <= tick_cnt + 1;
|
93 |
|
|
else
|
94 |
|
|
txd_int <= '1';
|
95 |
|
|
tick_cnt <= 0;
|
96 |
|
|
bit_cnt <= 0;
|
97 |
|
|
txr_state <= SM_SEND;
|
98 |
|
|
end if;
|
99 |
|
|
when SM_SEND =>
|
100 |
|
|
--for each bit, a one is 8 ticks low followed by 8 ticks high, and a zero is 8 ticks high followed by 8 ticks low
|
101 |
|
|
if tick_cnt < 8 then
|
102 |
|
|
txd_int <= not shifter(15);
|
103 |
|
|
tick_cnt <= tick_cnt + 1;
|
104 |
|
|
elsif tick_cnt < 15 then
|
105 |
|
|
txd_int <= shifter(15);
|
106 |
|
|
tick_cnt <= tick_cnt + 1;
|
107 |
|
|
else
|
108 |
|
|
txd_int <= shifter(15);
|
109 |
|
|
tick_cnt <= 0;
|
110 |
|
|
shifter <= shifter(14 downto 0) & '1';
|
111 |
|
|
--at end of this bit check to see if we have more bits or if it's time for the stop bit
|
112 |
|
|
if bit_cnt < 15 then
|
113 |
|
|
bit_cnt <= bit_cnt + 1;
|
114 |
|
|
else
|
115 |
|
|
bit_cnt <=0;
|
116 |
|
|
txr_state <= SM_STOP;
|
117 |
|
|
end if;
|
118 |
|
|
end if;
|
119 |
|
|
when SM_STOP =>
|
120 |
|
|
--stop bits are always ones, which are 8 ticks low followed by 8 ticks high
|
121 |
|
|
if tick_cnt < 8 then
|
122 |
|
|
txd_int <= '0';
|
123 |
|
|
tick_cnt <= tick_cnt + 1;
|
124 |
|
|
elsif tick_cnt < 15 then
|
125 |
|
|
txd_int <= '1';
|
126 |
|
|
tick_cnt <= tick_cnt + 1;
|
127 |
|
|
else
|
128 |
|
|
txd_int <= '1';
|
129 |
|
|
tick_cnt <= 0;
|
130 |
|
|
txr_state <= SM_IDLE;
|
131 |
|
|
end if;
|
132 |
|
|
--we should never get to the iothers state.
|
133 |
|
|
when others =>
|
134 |
|
|
tick_cnt <= 4;
|
135 |
|
|
bit_cnt <= 0;
|
136 |
|
|
txr_state <= SM_IDLE;
|
137 |
|
|
end case;
|
138 |
|
|
end if; --srst
|
139 |
|
|
end if; --clk16x
|
140 |
|
|
end process;
|
141 |
|
|
|
142 |
|
|
|
143 |
|
|
--An overrun error occurs when the transmit strobe is triggered and we are not finished with the previous state.
|
144 |
|
|
-- The error is cleared when the transmitter goes back to idle
|
145 |
|
|
p_or_err: process(clk16x)
|
146 |
|
|
begin
|
147 |
|
|
if rising_edge(clk16x) then
|
148 |
|
|
if srst = '1' then
|
149 |
|
|
err_int <='0';
|
150 |
|
|
elsif tx_stb = '1' and txr_state /= SM_IDLE then
|
151 |
|
|
err_int <= '1';
|
152 |
|
|
elsif txr_state = SM_IDLE then
|
153 |
|
|
err_int <= '0';
|
154 |
|
|
end if;
|
155 |
|
|
end if;
|
156 |
|
|
end process;
|
157 |
|
|
|
158 |
|
|
txd <= txd_int;
|
159 |
|
|
or_err <= err_int;
|
160 |
|
|
tx_idle <= '1' when txr_state = SM_IDLE else '0';
|
161 |
|
|
|
162 |
|
|
end rtl;
|