OpenCores
URL https://opencores.org/ocsvn/mblite/mblite/trunk

Subversion Repositories mblite

[/] [mblite/] [trunk/] [hw/] [core/] [core_wb.vhd] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 takar
----------------------------------------------------------------------------------------------
2
--
3
--      Input file         : core_wb.vhd
4
--      Design name        : core_wb
5
--      Author             : Tamar Kranenburg
6
--      Company            : Delft University of Technology
7
--                         : Faculty EEMCS, Department ME&CE
8
--                         : Systems and Circuits group
9
--
10
--      Description        : Top level module of the MB-Lite microprocessor with connected
11
--                           wishbone data bus
12
--
13
----------------------------------------------------------------------------------------------
14
 
15
LIBRARY ieee;
16
USE ieee.std_logic_1164.ALL;
17
USE ieee.std_logic_unsigned.ALL;
18
 
19
LIBRARY mblite;
20
USE mblite.config_Pkg.ALL;
21
USE mblite.core_Pkg.ALL;
22
USE mblite.std_Pkg.ALL;
23
 
24
ENTITY core_wb IS GENERIC
25
(
26
    G_INTERRUPT  : boolean := CFG_INTERRUPT;
27
    G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
28
    G_USE_BARREL : boolean := CFG_USE_BARREL;
29
    G_DEBUG      : boolean := CFG_DEBUG
30
);
31
PORT
32
(
33
    imem_o : OUT imem_out_type;
34
    wb_o   : OUT wb_mst_out_type;
35
    imem_i : IN imem_in_type;
36
    wb_i   : IN wb_mst_in_type
37
);
38
END core_wb;
39
 
40
ARCHITECTURE arch OF core_wb IS
41
    SIGNAL dmem_i : dmem_in_type;
42
    SIGNAL dmem_o : dmem_out_type;
43
BEGIN
44
 
45
    wb_adapter0 : core_wb_adapter PORT MAP
46
    (
47
        dmem_i => dmem_i,
48
        wb_o   => wb_o,
49
        dmem_o => dmem_o,
50
        wb_i   => wb_i
51
    );
52
 
53
    core0 : core GENERIC MAP
54
    (
55
        G_INTERRUPT  => G_INTERRUPT,
56
        G_USE_HW_MUL => G_USE_HW_MUL,
57
        G_USE_BARREL => G_USE_BARREL,
58
        G_DEBUG      => G_DEBUG
59
    )
60
    PORT MAP
61
    (
62
        imem_o => imem_o,
63
        dmem_o => dmem_o,
64
        imem_i => imem_i,
65
        dmem_i => dmem_i,
66
        int_i  => wb_i.int_i,
67
        rst_i  => wb_i.rst_i,
68
        clk_i  => wb_i.clk_i
69
    );
70
 
71
END arch;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.