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[/] [mblite/] [trunk/] [sw/] [util/] [bin2rom.c] - Blame information for rev 2

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Line No. Rev Author Line
1 2 takar
#include <stdio.h>
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#include <string.h>
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unsigned power(unsigned base,unsigned n) {
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  unsigned p;
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  for(p=1; n > 0; --n)
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     p=p*base;
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  return p;
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}
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int main(int argc, char *argv[]) {
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  FILE *infile, *outfile;
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  int c;
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  unsigned program_size;
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  unsigned i = 0;
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  if (argc != 4) {
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    print_help(argv[0]);
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    return(1);
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  }
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  infile = fopen(argv[1], "rb");
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  if (!infile) {
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    printf("Cannot open file %s\n", argv[1]);
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    return(1);
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  }
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  outfile = fopen(argv[2], "w");
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  if (!outfile) {
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    printf("Cannot open file %s\n", argv[2]);
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    return(1);
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  }
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  if (strlen(argv[3]) <= 0) {
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    printf("Argument depth missing", argv[3]);
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    return(1);
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  }
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  fprintf(outfile,"\
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----------------------------------------------------------------------------------------------\n\
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--\n\
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--      Input file         : pram.vhd\n\
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--      Design name        : pram\n\
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--      Author             : Tamar Kranenburg\n\
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--      Company            : Delft University of Technology\n\
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--\n\
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--      Description        : Single Port Synchronous Random Access Memory\n\
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--\n\
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----------------------------------------------------------------------------------------------\n\
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\n\
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LIBRARY ieee;\n\
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USE ieee.std_logic_1164.ALL;\n\
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USE ieee.std_logic_unsigned.ALL;\n\
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\n\
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LIBRARY mblite;\n\
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USE mblite.std_Pkg.ALL;\n\
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\n\
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ENTITY pram IS\n\
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    GENERIC\n\
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    (\n\
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        WIDTH : integer := 32;\n\
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        SIZE  : integer := %s\n\
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    );\n\
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    PORT\n\
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    (\n\
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        dat_o                   : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);\n\
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        dat_i                   : IN std_logic_vector(WIDTH - 1 DOWNTO 0);\n\
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        adr_i                   : IN std_logic_vector(SIZE - 1 DOWNTO 0);\n\
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        wre_i                   : IN std_logic;\n\
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        ena_i                   : IN std_logic;\n\
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        clk_i                   : IN std_logic\n\
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    );\n\
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END pram;\n\
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\n\
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ARCHITECTURE arch OF pram IS\n\
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  TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_logic_vector(WIDTH - 1 DOWNTO 0);\n\
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  SIGNAL ram : ram_type := (", argv[3]);
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  while((c = fgetc(infile)) != EOF)
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  {
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    if ((i % 32) == 0 ) { fprintf(outfile,"\n    "); }
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    if ((i % 4) == 0 ) { fprintf(outfile,"X\""); }
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    fprintf(outfile,"%.2X", (unsigned char) c & 0x0ff);
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    if ((i % 4) == 3 ) { fprintf(outfile,"\","); }
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    i++;
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  }
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  fprintf(outfile, "X\"FFFFFFFF\"");
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  i+=4;
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  /* Fill rest of ram */
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  program_size = power(2, atoi(argv[3])) * 4;
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  while(i < program_size)
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  {
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    if ((i % 4) == 0 ) { fprintf(outfile,","); }
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    if ((i % 32) == 0 ) { fprintf(outfile,"\n    "); }
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    if ((i % 4) == 0 ) { fprintf(outfile,"X\""); }
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    fprintf(outfile,"00");
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    if ((i % 4) == 3 ) { fprintf(outfile,"\""); }
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    i++;
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  }
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  fprintf(outfile,");\n\
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\n\
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BEGIN\n\
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    PROCESS(clk_i)\n\
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    BEGIN\n\
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        IF rising_edge(clk_i) THEN\n\
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            IF notx(adr_i) AND ena_i = '1' THEN\n\
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                IF wre_i = '1' THEN\n\
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                    ram(conv_integer(adr_i)) <= dat_i;\n\
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                END IF;\n\
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                dat_o <= ram(conv_integer(adr_i));\n\
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            END IF;\n\
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        END IF;\n\
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    END PROCESS;\n\
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END arch;\n\
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");
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  fclose(infile);
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  fclose(outfile);
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  return 0;
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}
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int print_help(char * name)
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{
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  fprintf(stderr, "Usage: %s INFILE OUTFILE WIDTH DEPTH\n", name);
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  fprintf(stderr, "%s converts a binary into a VHDL rom file\n", name);
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  fprintf(stderr, "DEPTH in log(n) elements\n");
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  return 0;
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}

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