OpenCores
URL https://opencores.org/ocsvn/mblite/mblite/trunk

Subversion Repositories mblite

[/] [mblite/] [trunk/] [tb/] [rom_sw.mem] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 takar 
// memory data file (do not edit the following line - required for mem load use)
2 
// SB R20, R0, R4
3 
// SB R20, R0, R5
4 
// SB R20, R0, R6
5 
// SB R20, R0, R7
6 
// SH R20, R0, R4
7 
// SH R20, R0, R6
8 
// SW R20, R0, R4
9 
// NOP
10 
// NOP
11 
// IMM FFFF             // Set IMM to negative
12 
// ADDI R1, R20, 1000   // Imm value must be negative: R1 = FFFF1000 + 0000F0F1 = 000000F1
13 
// IMM 0                // Set IMM to zero
14 
// ADDI R1, R20, F000   // Imm value must be positive: R1 = 0000F000 + 0000F0F1 = 0001E0F1
15 
// SWI R1, R10, 0       // Fwd on REG D
16 
// NOP
17 
// IMM FFFF             // Set IMM to negative
18 
// ADDI R1, R20, 1000   // Imm value must be positive: R1 = FFFF1000 + 0000F0F1 = 000000F1
19 
// NOP
20 
// SWI R1, R10, 0       // Store F1 to MEM[R10]
21 
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1
22 
@00000000
23 
D2802000
24 
D2802800
25 
D2803000
26 
D2803800
27 
D6802000
28 
D6803000
29 
DA802000
30 
00000000
31 
00000000
32 
B000FFFF
33 
20341000
34 
B0000000
35 
2034F000
36 
F82A0000
37 
00000000
38 
B000FFFF
39 
20341000
40 
00000000
41 
F82A0000
42 
00000000
43 
00000000
44 
00000000

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.