Subversion Repositories memory_cores

<!--# set var="title" value="" -->

<!--# include virtual="/ssi/ssi_start.shtml" -->

<b><font size=+2 face="Helvetica, Arial" color=#bf0000>Project Name: Memory cores</font></b><p><font size=+1><b>Description</b></font><p>Check the memory cores site for more documentation at<a href="http://www.geocities.com/SiliconValley/Pines/6639/ip/memory_cores.html">Jamil Khatib site</a></ul>

<p>Current Status:<ul>

<li>VHDL codes are stable and available on the CVS</a></li>

<li>Some cores need test benchs</a></li>

<li>we need more memory cores with different features</a></li>

<li>we need more people to test the cores on real hardware</a></li>

<li> You can download the memory codes from the CVS using the module name "memory_cores" and for new cores use module name "memory_cores2".</li>

<li><a href="http://www.opencores.org/cgi-bin/cvsget.cgi/memory_cores">Download Old memory cores </a>(have some features that still not available in the new cores.</li>

<li><a href="http://www.opencores.org/cgi-bin/cvsget.cgi/memory_cores2">Download memory cores files</a></li>

<li><a href="http://www.opencores.org/cgi-bin/cvsget.cgi/memory_cores/dpmem">Download Dual port memory core</a> Includes WISHBONE compatible interface core wrapper. The core uses single or dual clocks and other parametrizable cofigurations </li>

<li><a href="http://www.opencores.org/cgi-bin/cvsget.cgi/memory_cores/spmem">Download Single port memory core</a> Includes WISHBONE compatible interface core wrapper. The core has several parametrizable cofigurations</li>

<li><a href="http://www.opencores.org/cgi-bin/cvsget.cgi/memory_cores/fifo">Download fifo buffer</a></li>

<li> Note: it is recommended to download the whole module because files are dependent on each other</li>

</ul>

<p>Maintainer(s):<ul>Jamil Khatib</ul><p>Author(s):<ul>Jamil Khatib</ul><p>Mailing-list:<ul><a href=mailto:khatib@ieee.org_NOSPAM>Jamil Khatib</a></ul><!--# include virtual="/ssi/ssi_end.shtml" -->