OpenCores
URL https://opencores.org/ocsvn/mesi_isc/mesi_isc/trunk

Subversion Repositories mesi_isc

[/] [mesi_isc/] [trunk/] [src/] [rtl/] [mesi_isc_breq_fifos_cntl.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 yaira
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
//////////////////////////////////////////////////////////////////////
29
////                                                              ////
30
////  MESI_ISC Project                                            ////
31
////                                                              ////
32
////  Author(s):                                                  ////
33
////      - Yair Amitay       yair.amitay@yahoo.com               ////
34
////                          www.linkedin.com/in/yairamitay      ////
35
////                                                              ////
36
////  Description                                                 ////
37
////  mesi_isc_breq_fifos_cntl                                    ////
38
////  -------------------                                         ////
39
////  Controls and muxes of the mesi_isc_breq_fifos. This module  ////
40
////  contains all the controls and logic of the                  ////
41
////  mesi_isc_breq_fifos_cntl                                    ////
42
////                                                              ////
43
////  To Do:                                                      ////
44
////   -                                                          ////
45
////                                                              ////
46
//////////////////////////////////////////////////////////////////////
47
 
48
`include "mesi_isc_define.v"
49
 
50
module mesi_isc_breq_fifos_cntl
51
    (
52
     // Inputs
53
     clk,
54
     rst,
55
     mbus_cmd_array_i,
56
     fifo_status_empty_array_i,
57
     fifo_status_full_array_i,
58
     broad_fifo_status_full_i,
59
     broad_addr_array_i,
60
     broad_type_array_i,
61
     broad_id_array_i,
62
     // Outputs
63
     mbus_ack_array_o,
64
     fifo_wr_array_o,
65
     fifo_rd_array_o,
66
     broad_fifo_wr_o,
67
     broad_addr_o,
68
     broad_type_o,
69
     broad_cpu_id_o,
70
     broad_id_o,
71
     breq_type_array_o,
72
     breq_cpu_id_array_o,
73
     breq_id_array_o
74
   );
75
 
76
parameter
77
  MBUS_CMD_WIDTH           = 3,
78
  ADDR_WIDTH               = 32,
79
  BROAD_TYPE_WIDTH         = 2,
80
  BROAD_ID_WIDTH           = 7;
81
 
82
// Inputs
83
//================================
84
// System
85
input                   clk;          // System clock
86
input                   rst;          // Active high system reset
87
 
88
// Main buses
89
// The mbus commands, according to the commend the breq are written to
90
// the fifos
91
input [4*MBUS_CMD_WIDTH-1:0] mbus_cmd_array_i;
92
// cntl
93
// breq fifo status
94
input [3:0]             fifo_status_empty_array_i;
95
input [3:0]             fifo_status_full_array_i;
96
// broad_fifo
97
// breqs can be written to the broad fifo when it is not full
98
input                   broad_fifo_status_full_i;
99
// mux
100
// The mux sends to the broad fifo one of the broad from the 4 breq fifos.
101
// It sends: address. type, cpu_id, broad_id
102
input [4*ADDR_WIDTH-1      :0] broad_addr_array_i;
103
input [4*BROAD_TYPE_WIDTH-1:0] broad_type_array_i;
104
input [4*BROAD_ID_WIDTH-1  :0] broad_id_array_i;
105
 
106
// Outputs
107
// Main busses
108
// When a breq is stored to a fifo an acknowledge is send to the initiator
109
output [3:0]            mbus_ack_array_o;
110
// cntl
111
// Write the breq to one of the fifos
112
output [3:0]            fifo_wr_array_o;
113
// Read a breq toward the broad fifo
114
output [3:0]            fifo_rd_array_o;
115
// broad_fifo
116
// Command to fifo for a broad in the broad fifo
117
output                  broad_fifo_wr_o;
118
// The broad information that is send to the broad fifo: address. type, cpu_id
119
// and broad_id
120
output [ADDR_WIDTH-1      :0] broad_addr_o;
121
output [BROAD_TYPE_WIDTH-1:0] broad_type_o;
122
output [1:0]                  broad_cpu_id_o;
123
output [BROAD_ID_WIDTH-1:  0] broad_id_o;
124
// fifo inputs
125
// Some of the breq fifo input are manipulate before storing
126
// The type in manipulation of the mbus command
127
output [4*BROAD_TYPE_WIDTH-1:0] breq_type_array_o;
128
// Each CPU has a fixed ID
129
output [4*2-1:0]              breq_cpu_id_array_o;
130
// Each breq has a unique ID.
131
output [4*BROAD_ID_WIDTH-1:0] breq_id_array_o;
132
 
133
// Regs & wires
134
//================================
135
reg [3:0]               mbus_ack_array;
136
reg [3:0]               fifos_priority; // A one hot priority between the 
137
                                      // breq fifos toward the broad fifo
138
wire [3:0]              fifos_priority_barrel_shiftl_1,
139
                        fifos_priority_barrel_shiftl_2,
140
                        fifos_priority_barrel_shiftl_3;
141
wire [3:0]              fifo_select_oh; // A one hot control of the mux between
142
                                        // breq fifos toward the broad fifo
143
reg  [BROAD_ID_WIDTH-3:0] breq_id_base; // breq_id_base is the base value of
144
                                        // the IDs. breq_id_base = breq_id/4
145
 
146
wire [MBUS_CMD_WIDTH-1:0] mbus_cmd_array_i_3,
147
                          mbus_cmd_array_i_2,
148
                          mbus_cmd_array_i_1,
149
                          mbus_cmd_array_i_0;
150
reg [4*BROAD_TYPE_WIDTH-1:0] breq_type_array_o;
151
 
152
// Assigns for outputs
153
//================================
154
assign mbus_ack_array_o   = mbus_ack_array;
155
 
156
 
157
// fifo_rd_array_o, broad_fifo_wr_o
158
// Read the breq from one of the breq fifos and write it to the broad fifo.   
159
assign fifo_rd_array_o = {4{~broad_fifo_status_full_i}} & // There is space in
160
                                      // the broad fifo
161
                         fifo_select_oh[3:0]; // The highest priority
162
                                      // fifo that has a valid breq.
163
assign broad_fifo_wr_o = |fifo_rd_array_o[3:0]; // Write to the broad fifo is 
164
                                      // done in parallel to Read from one of
165
                                      // the breq fifo The values set
166
 
167
// fifos_priority, fifos_priority_barrel_shift_1/2/3 (one hot)
168
// The priority between the CPU is done in round robin order.
169
// The breq which is sent to the broad fifo is selected according to 
170
// the value of the fifos_priority register, from the low value to the high 
171
// value.
172
// For example when fifos_priority == 2 then the priority order is:
173
//  2 -> 3 -> 0 -> 1. The breq is sent from the first breq fifo, in that order,
174
// that has a valid breq.
175
// The priority is change whenever a breq is sent to the broad fifo  
176
always @(posedge clk or posedge rst)
177
 if (rst)
178
   fifos_priority <= 1;
179
 else if (broad_fifo_wr_o)
180
   fifos_priority[3:0] <= fifos_priority_barrel_shiftl_1[3:0];
181
 
182
assign fifos_priority_barrel_shiftl_3[3:0] =
183
                                    {fifos_priority[0]  , fifos_priority[3:1]};
184
assign fifos_priority_barrel_shiftl_2[3:0] =
185
                                    {fifos_priority[1:0], fifos_priority[3:2]};
186
assign fifos_priority_barrel_shiftl_1[3:0] =
187
                                    {fifos_priority[2:0], fifos_priority[3]};
188
 
189
// fifo_select_oh (one hot)
190
// Points to the highest priority fifo (see fifos_priority) that
191
// has a valid breq.
192
// The control of the mux from the breq fifos to the broad fifo.
193
assign fifo_select_oh[3:0] =
194
          // If the 1st highest priority fifo is not empty then select it
195
          // Or the bit-wise results of the following formula to one result   
196
          // Bit-wise set for fifos that are not empty 
197
          |(~fifo_status_empty_array_i[3:0] &
198
             // Bit-wise one hot priority for the 1st highest priority
199
             fifos_priority[3:0]                 ) ?
200
                                          fifos_priority[3:0]                 :
201
          |(~fifo_status_empty_array_i[3:0] &
202
             fifos_priority_barrel_shiftl_1[3:0] ) ?
203
                                          fifos_priority_barrel_shiftl_1[3:0] :
204
          |(~fifo_status_empty_array_i[3:0] &
205
             fifos_priority_barrel_shiftl_2[3:0] ) ?
206
                                          fifos_priority_barrel_shiftl_2[3:0] :
207
          |(~fifo_status_empty_array_i[3:0] &
208
             fifos_priority_barrel_shiftl_3[3:0] ) ?
209
                                          fifos_priority_barrel_shiftl_3[3:0] :
210
                                          4'd0;
211
 
212
// broad_addr_o, broad_type_o, broad_cpu_id_o, broad_id_o
213
// One hot mux
214
assign broad_addr_o[ADDR_WIDTH-1:0] =
215
            broad_addr_array_i[(3+1)*ADDR_WIDTH-1 : 3*ADDR_WIDTH] &
216
                                              {ADDR_WIDTH{fifo_select_oh[3]}} |
217
            broad_addr_array_i[(2+1)*ADDR_WIDTH-1 : 2*ADDR_WIDTH] &
218
                                              {ADDR_WIDTH{fifo_select_oh[2]}} |
219
            broad_addr_array_i[(1+1)*ADDR_WIDTH-1 : 1*ADDR_WIDTH] &
220
                                              {ADDR_WIDTH{fifo_select_oh[1]}} |
221
            broad_addr_array_i[(0+1)*ADDR_WIDTH-1 : 0*ADDR_WIDTH] &
222
                                              {ADDR_WIDTH{fifo_select_oh[0]}};
223
assign broad_type_o[BROAD_TYPE_WIDTH-1:0] =
224
            broad_type_array_i[(3+1)*BROAD_TYPE_WIDTH-1 : 3*BROAD_TYPE_WIDTH] &
225
                                        {BROAD_TYPE_WIDTH{fifo_select_oh[3]}} |
226
            broad_type_array_i[(2+1)*BROAD_TYPE_WIDTH-1 : 2*BROAD_TYPE_WIDTH] &
227
                                        {BROAD_TYPE_WIDTH{fifo_select_oh[2]}} |
228
            broad_type_array_i[(1+1)*BROAD_TYPE_WIDTH-1 : 1*BROAD_TYPE_WIDTH] &
229
                                        {BROAD_TYPE_WIDTH{fifo_select_oh[1]}} |
230
            broad_type_array_i[(0+1)*BROAD_TYPE_WIDTH-1 : 0*BROAD_TYPE_WIDTH] &
231
                                        {BROAD_TYPE_WIDTH{fifo_select_oh[0]}};
232
// Each CPU has a fixed ID
233
assign broad_cpu_id_o[1:0] = 2'd3 & {2{fifo_select_oh[3]}} |
234
                             2'd2 & {2{fifo_select_oh[2]}} |
235
                             2'd1 & {2{fifo_select_oh[1]}} |
236
                             2'd0 & {2{fifo_select_oh[0]}};
237
 
238
assign broad_id_o[BROAD_ID_WIDTH-1:0] =
239
            broad_id_array_i[(3+1)*BROAD_ID_WIDTH-1 : 3*BROAD_ID_WIDTH] &
240
                                          {BROAD_ID_WIDTH{fifo_select_oh[3]}} |
241
            broad_id_array_i[(2+1)*BROAD_ID_WIDTH-1 : 2*BROAD_ID_WIDTH] &
242
                                          {BROAD_ID_WIDTH{fifo_select_oh[2]}} |
243
            broad_id_array_i[(1+1)*BROAD_ID_WIDTH-1 : 1*BROAD_ID_WIDTH] &
244
                                          {BROAD_ID_WIDTH{fifo_select_oh[1]}} |
245
            broad_id_array_i[(0+1)*BROAD_ID_WIDTH-1 : 0*BROAD_ID_WIDTH] &
246
                                          {BROAD_ID_WIDTH{fifo_select_oh[0]}};
247
 
248
//fifo_wr_array
249
// Write the breq into the fifo.
250
// When an acknowledge is sent to the mbus the breq is written to the fifo.
251
assign fifo_wr_array_o[3:0] = mbus_ack_array[3:0];
252
 
253
// mbus_ack_array
254
// The mbus ack is an indication for the mbus that the (broadcast) transaction
255
// was received and it can proceed to the next transaction (or to nop).
256
// The acknowledge is sent to the mbus when the breq can be stored in the fifo.
257
// The acknowledge can't be asserted for more then one cycle for simplification
258
// of the protocol and timing paths. 
259
always @(posedge clk or posedge rst)
260
  if (rst)
261
     mbus_ack_array[3:0] <= 0;
262
  else
263
  begin
264
     mbus_ack_array[3] <= ~mbus_ack_array[3] &
265
                          (mbus_cmd_array_i_3 == `MESI_ISC_MBUS_CMD_WR_BROAD |
266
                           mbus_cmd_array_i_3 == `MESI_ISC_MBUS_CMD_RD_BROAD )&
267
                          fifo_status_full_array_i[3] == 0;
268
     mbus_ack_array[2] <= ~mbus_ack_array[2] &
269
                          (mbus_cmd_array_i_2 == `MESI_ISC_MBUS_CMD_WR_BROAD |
270
                           mbus_cmd_array_i_2 == `MESI_ISC_MBUS_CMD_RD_BROAD )&
271
                          fifo_status_full_array_i[2] == 0;
272
     mbus_ack_array[1] <= ~mbus_ack_array[1] &
273
                          (mbus_cmd_array_i_1 == `MESI_ISC_MBUS_CMD_WR_BROAD |
274
                           mbus_cmd_array_i_1 == `MESI_ISC_MBUS_CMD_RD_BROAD )&
275
                          fifo_status_full_array_i[1] == 0;
276
     mbus_ack_array[0] <= ~mbus_ack_array[0] &
277
                          (mbus_cmd_array_i_0 == `MESI_ISC_MBUS_CMD_WR_BROAD |
278
                           mbus_cmd_array_i_0 == `MESI_ISC_MBUS_CMD_RD_BROAD )&
279
                          fifo_status_full_array_i[0] == 0;
280
 
281
  end
282
 
283
assign mbus_cmd_array_i_3[MBUS_CMD_WIDTH-1:0] =
284
                   mbus_cmd_array_i[(3+1)*MBUS_CMD_WIDTH-1 : 3*MBUS_CMD_WIDTH];
285
assign mbus_cmd_array_i_2[MBUS_CMD_WIDTH-1:0] =
286
                   mbus_cmd_array_i[(2+1)*MBUS_CMD_WIDTH-1 : 2*MBUS_CMD_WIDTH];
287
assign mbus_cmd_array_i_1[MBUS_CMD_WIDTH-1:0] =
288
                   mbus_cmd_array_i[(1+1)*MBUS_CMD_WIDTH-1 : 1*MBUS_CMD_WIDTH];
289
assign mbus_cmd_array_i_0[MBUS_CMD_WIDTH-1:0] =
290
                   mbus_cmd_array_i[(0+1)*MBUS_CMD_WIDTH-1 : 0*MBUS_CMD_WIDTH];
291
 
292
// The breq type depends on the mbus command.
293
// Mbus: Write broadcast - breq type: wr
294
// Mbus: Read broadcast  - breq type: rd
295
// Mbus: else            - breq type: nop
296
always @(posedge clk or posedge rst)
297
 if (rst)
298
   breq_type_array_o[4*BROAD_TYPE_WIDTH-1:0] <= 0;
299
 else begin
300
       //                \ /                      \ /
301
       breq_type_array_o[(3+1)*BROAD_TYPE_WIDTH-1: 3*BROAD_TYPE_WIDTH] =
302
        //              \ /
303
        mbus_cmd_array_i_3[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_WR_BROAD ?
304
                                                     `MESI_ISC_BREQ_TYPE_WR:
305
        //              \ /
306
        mbus_cmd_array_i_3[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_RD_BROAD ?
307
                                                     `MESI_ISC_BREQ_TYPE_RD:
308
                                                     `MESI_ISC_BREQ_TYPE_NOP;
309
       //                \ /                      \ /
310
       breq_type_array_o[(2+1)*BROAD_TYPE_WIDTH-1: 2*BROAD_TYPE_WIDTH] =
311
        //              \ /
312
        mbus_cmd_array_i_2[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_WR_BROAD ?
313
                                                     `MESI_ISC_BREQ_TYPE_WR:
314
        //              \ /
315
        mbus_cmd_array_i_2[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_RD_BROAD ?
316
                                                     `MESI_ISC_BREQ_TYPE_RD:
317
                                                     `MESI_ISC_BREQ_TYPE_NOP;
318
       //                \ /                      \ /
319
       breq_type_array_o[(1+1)*BROAD_TYPE_WIDTH-1: 1*BROAD_TYPE_WIDTH] =
320
        //              \ /
321
        mbus_cmd_array_i_1[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_WR_BROAD ?
322
                                                     `MESI_ISC_BREQ_TYPE_WR:
323
        //              \ /
324
        mbus_cmd_array_i_1[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_RD_BROAD ?
325
                                                     `MESI_ISC_BREQ_TYPE_RD:
326
                                                     `MESI_ISC_BREQ_TYPE_NOP;
327
       //                \ /                      \ /
328
       breq_type_array_o[(0+1)*BROAD_TYPE_WIDTH-1: 0*BROAD_TYPE_WIDTH] =
329
        //              \ /
330
        mbus_cmd_array_i_0[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_WR_BROAD ?
331
                                                     `MESI_ISC_BREQ_TYPE_WR:
332
        //              \ /
333
        mbus_cmd_array_i_0[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_RD_BROAD ?
334
                                                     `MESI_ISC_BREQ_TYPE_RD:
335
                                                     `MESI_ISC_BREQ_TYPE_NOP;
336
 
337
end
338
// The CPU IDs have fixed values
339
assign breq_cpu_id_array_o[(3+1)*2-1 : 3*2] = 3;
340
assign breq_cpu_id_array_o[(2+1)*2-1 : 2*2] = 2;
341
assign breq_cpu_id_array_o[(1+1)*2-1 : 1*2] = 1;
342
assign breq_cpu_id_array_o[(0+1)*2-1 : 0*2] = 0;
343
 
344
// breq_id_array_o
345
// In a cycle that at least on breq is received there are 4 unique numbers -
346
// one for each fifo. These numbers are the breq ID. In a cycle that a certain
347
// fifo does not receive a breq (but there is at least one more fifos that  
348
// receives) then its unique number in that cycle is not used.
349
// The values of breq_id are cyclic and every specific amount of breqs its  
350
// value go back to 0. The possible different values of breq_id are much bigger
351
// then 4*(the latency of mesi_isc). In that way it is not possible that the
352
// same ID is used for more then one request in the same time.
353
// 
354
// fifo 0 ID (for each cycle) is breq_id_base*4
355
// fifo 1 ID is breq_id_base*4 + 1
356
// fifo 1 ID is breq_id_base*4 + 2
357
// fifo 1 ID is breq_id_base*4 + 3
358
assign breq_id_array_o[(3+1)*BROAD_ID_WIDTH-1 : 3*BROAD_ID_WIDTH] =
359
                                   {breq_id_base[BROAD_ID_WIDTH-3 : 0], 2'b00};
360
assign breq_id_array_o[(2+1)*BROAD_ID_WIDTH-1 : 2*BROAD_ID_WIDTH] =
361
                                   {breq_id_base[BROAD_ID_WIDTH-3 : 0], 2'b01};
362
assign breq_id_array_o[(1+1)*BROAD_ID_WIDTH-1 : 1*BROAD_ID_WIDTH] =
363
                                   {breq_id_base[BROAD_ID_WIDTH-3 : 0], 2'b10};
364
assign breq_id_array_o[(0+1)*BROAD_ID_WIDTH-1 : 0*BROAD_ID_WIDTH] =
365
                                   {breq_id_base[BROAD_ID_WIDTH-3 : 0], 2'b11};
366
 
367
// The least significant bits of breq_id_base are always 0
368
always @(posedge clk or posedge rst)
369
 if (rst)
370
   breq_id_base[BROAD_ID_WIDTH-3 : 0] <= 0;
371
 else if (|fifo_wr_array_o)
372
  //  breq_id_base+1 is analogous to  breq_id+4
373
  breq_id_base[BROAD_ID_WIDTH-3 : 0] <= breq_id_base[BROAD_ID_WIDTH-3 : 0] + 1;
374
 
375
endmodule
376
 

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.