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[/] [mesi_isc/] [trunk/] [src/] [rtl/] [mesi_isc_broad.v] - Blame information for rev 2

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1 2 yaira
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  MESI_ISC Project                                            ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Yair Amitay       yair.amitay@yahoo.com               ////
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////                          www.linkedin.com/in/yairamitay      ////
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////                                                              ////
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////  Description                                                 ////
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////  mesi_isc_broad                                              ////
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////  -------------------                                         ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "mesi_isc_define.v"
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module mesi_isc_broad
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    (
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     // Inputs
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     clk,
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     rst,
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     cbus_ack_array_i,
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     broad_fifo_wr_i,
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     broad_addr_i,
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     broad_type_i,
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     broad_cpu_id_i,
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     broad_id_i,
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     // Outputs
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     cbus_addr_o,
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     cbus_cmd_array_o,
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     fifo_status_full_o
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     );
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parameter
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  CBUS_CMD_WIDTH           = 3,
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  ADDR_WIDTH               = 32,
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  BROAD_TYPE_WIDTH         = 2,
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  BROAD_ID_WIDTH           = 5,
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  BROAD_REQ_FIFO_SIZE      = 4,
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  BROAD_REQ_FIFO_SIZE_LOG2 = 2;
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// Inputs
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//================================
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// System
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input                   clk;          // System clock
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input                   rst;          // Active high system reset
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// Coherence bus
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input [3:0]             cbus_ack_array_i;
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input                   broad_fifo_wr_i; // Write the broadcast request
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input [ADDR_WIDTH-1:0]  broad_addr_i; // Broad addresses
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input [BROAD_TYPE_WIDTH-1:0] broad_type_i; // Broad type
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input [1:0]             broad_cpu_id_i; // Initiators
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                                      // CPU id array
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input [BROAD_ID_WIDTH-1:0] broad_id_i; // Broadcast request ID array
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// Outputs
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//================================
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output [ADDR_WIDTH-1:0] cbus_addr_o;  // Coherence bus address. All busses have
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                                     // the same address
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output [4*CBUS_CMD_WIDTH-1:0] cbus_cmd_array_o; // See broad_addr_i
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output                  fifo_status_full_o; // The broad fifo is full
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// Regs & wires
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//================================
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wire                    broad_fifo_rd; // Read broadcast
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wire                    fifo_status_empty; // Status empty
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wire                    fifo_status_full; // The broad fifo is full
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wire [ADDR_WIDTH-1:0]   broad_snoop_addr; // Address of broadcast snooping
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wire [BROAD_TYPE_WIDTH-1:0] broad_snoop_type;  // Type of broadcast snooping
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wire [1:0]              broad_snoop_cpu_id; // ID of initiator of broadcast
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                                          // snooping
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wire [BROAD_ID_WIDTH-1:0] broad_snoop_id; // Broadcast snooping ID
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\
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// assign
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//================================
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assign cbus_addr_o[ADDR_WIDTH-1:0] = broad_snoop_addr[ADDR_WIDTH-1:0];
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assign fifo_status_full_o = fifo_status_full;
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// Breq fifo control
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//================================
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mesi_isc_broad_cntl #(CBUS_CMD_WIDTH,
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                      BROAD_TYPE_WIDTH,
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                      BROAD_ID_WIDTH)
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   mesi_isc_broad_cntl
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    (
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     // Inputs
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     .clk                   (clk),
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     .rst                   (rst),
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     // Coherence buses
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     .cbus_ack_array_i      (cbus_ack_array_i[3:0]),
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     // broad_fifo
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     .fifo_status_empty_i   (fifo_status_empty),
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     .fifo_status_full_i    (fifo_status_full),
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     // broad_fifo
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     .broad_snoop_type_i    (broad_snoop_type[BROAD_TYPE_WIDTH-1:0]),
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     .broad_snoop_cpu_id_i  (broad_snoop_cpu_id[1:0]),
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     .broad_snoop_id_i      (broad_snoop_id[BROAD_ID_WIDTH-1:0]),
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     // Outputs
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     // Coherence buses
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     .cbus_cmd_array_o      (cbus_cmd_array_o[4*CBUS_CMD_WIDTH-1:0]),
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     // fifo
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     .broad_fifo_rd_o       (broad_fifo_rd)
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     );
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// broad fifo
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//================================
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mesi_isc_basic_fifo #(ADDR_WIDTH         +       // DATA_WIDTH
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                      BROAD_TYPE_WIDTH   +
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                      2                  +       // BROAD_CPU_ID_WIDTH
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                      BROAD_ID_WIDTH,
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                      BROAD_REQ_FIFO_SIZE,       // FIFO_SIZE
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                      BROAD_REQ_FIFO_SIZE_LOG2)  // FIFO_SIZE_LOG2
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   //  \ /  (\ / marks the fifo ID) 
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   broad_fifo
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    (
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     // Inputs
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     .clk                   (clk),
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     .rst                   (rst),
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     .wr_i                  (broad_fifo_wr_i),
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     .rd_i                  (broad_fifo_rd),
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     .data_i                ({broad_addr_i[ADDR_WIDTH-1:0],
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                              broad_type_i[BROAD_TYPE_WIDTH-1:0],
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                              broad_cpu_id_i[1:0],
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                              broad_id_i[BROAD_ID_WIDTH-1:0]
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                             }),
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     // Outputs
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     .data_o                ({broad_snoop_addr[ADDR_WIDTH-1:0],
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                              broad_snoop_type[BROAD_TYPE_WIDTH-1:0],
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                              broad_snoop_cpu_id[1:0],
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                              broad_snoop_id[BROAD_ID_WIDTH-1:0]
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                             }),
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     .status_empty_o        (fifo_status_empty),
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     .status_full_o         (fifo_status_full)
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     );
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endmodule
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