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[/] [mesi_isc/] [trunk/] [syn/] [mesi_isc.tcl] - Blame information for rev 4

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# Copyright (C) 1991-2012 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions 
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# and other software and tools, and its AMPP partner logic 
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# functions, and any output files from any of the foregoing 
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# (including device programming or simulation files), and any 
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# associated documentation or information are expressly subject 
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# to the terms and conditions of the Altera Program License 
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# Subscription Agreement, Altera MegaCore Function License 
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# Agreement, or other applicable license agreement, including, 
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# without limitation, that your use is for the sole purpose of 
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# programming logic devices manufactured by Altera and sold by 
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# Altera or its authorized distributors.  Please refer to the 
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# applicable agreement for further details.
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# Quartus II: Generate Tcl File for Project
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# File: mesi_isc.tcl
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# Generated on: Tue Dec 25 13:58:34 2012
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# Load Quartus II Tcl Project package
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package require ::quartus::project
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set need_to_close_project 0
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set make_assignments 1
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# Check that the right project is open
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if {[is_project_open]} {
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        if {[string compare $quartus(project) "mesi_isc"]} {
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                puts "Project mesi_isc is not open"
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                set make_assignments 0
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        }
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} else {
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        # Only open if not already open
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        if {[project_exists mesi_isc]} {
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                project_open -revision mesi_isc mesi_isc
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        } else {
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                project_new -revision mesi_isc mesi_isc
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        }
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        set need_to_close_project 1
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}
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# Make assignments
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if {$make_assignments} {
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        set_global_assignment -name FAMILY "Cyclone IV GX"
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        set_global_assignment -name DEVICE auto
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        set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.0 SP2"
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        set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:58:58  NOVEMBER 06, 2012"
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        set_global_assignment -name LAST_QUARTUS_VERSION "12.0 SP2"
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        set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_define.v
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        set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_broad_cntl.v
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        set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_broad.v
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        set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_breq_fifos_cntl.v
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        set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_breq_fifos.v
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        set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_basic_fifo.v
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        set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc.v
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        set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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        set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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        set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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        set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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        # Commit assignments
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        export_assignments
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        # Close project
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        if {$need_to_close_project} {
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                project_close
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        }
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}

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