1 |
4 |
yaira |
Flow Summary report for mesi_isc
|
2 |
|
|
Tue Nov 6 20:48:09 2012
|
3 |
|
|
Quartus II 32-bit Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition
|
4 |
|
|
|
5 |
|
|
|
6 |
|
|
---------------------
|
7 |
|
|
; Table of Contents ;
|
8 |
|
|
---------------------
|
9 |
|
|
1. Legal Notice
|
10 |
|
|
2. Flow Summary
|
11 |
|
|
|
12 |
|
|
|
13 |
|
|
|
14 |
|
|
----------------
|
15 |
|
|
; Legal Notice ;
|
16 |
|
|
----------------
|
17 |
|
|
Copyright (C) 1991-2012 Altera Corporation
|
18 |
|
|
Your use of Altera Corporation's design tools, logic functions
|
19 |
|
|
and other software and tools, and its AMPP partner logic
|
20 |
|
|
functions, and any output files from any of the foregoing
|
21 |
|
|
(including device programming or simulation files), and any
|
22 |
|
|
associated documentation or information are expressly subject
|
23 |
|
|
to the terms and conditions of the Altera Program License
|
24 |
|
|
Subscription Agreement, Altera MegaCore Function License
|
25 |
|
|
Agreement, or other applicable license agreement, including,
|
26 |
|
|
without limitation, that your use is for the sole purpose of
|
27 |
|
|
programming logic devices manufactured by Altera and sold by
|
28 |
|
|
Altera or its authorized distributors. Please refer to the
|
29 |
|
|
applicable agreement for further details.
|
30 |
|
|
|
31 |
|
|
|
32 |
|
|
|
33 |
|
|
+------------------------------------------------------------------------------------+
|
34 |
|
|
; Flow Summary ;
|
35 |
|
|
+------------------------------------+-----------------------------------------------+
|
36 |
|
|
; Flow Status ; Successful - Tue Nov 6 14:54:24 2012 ;
|
37 |
|
|
; Quartus II 32-bit Version ; 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition ;
|
38 |
|
|
; Revision Name ; mesi_isc ;
|
39 |
|
|
; Top-level Entity Name ; mesi_isc ;
|
40 |
|
|
; Family ; Cyclone IV GX ;
|
41 |
|
|
; Total logic elements ; 72 / 29,440 ( < 1 % ) ;
|
42 |
|
|
; Total combinational functions ; 72 / 29,440 ( < 1 % ) ;
|
43 |
|
|
; Dedicated logic registers ; 45 / 29,440 ( < 1 % ) ;
|
44 |
|
|
; Total registers ; 45 ;
|
45 |
|
|
; Total pins ; 190 / 307 ( 62 % ) ;
|
46 |
|
|
; Total virtual pins ; 0 ;
|
47 |
|
|
; Total memory bits ; 0 / 1,105,920 ( 0 % ) ;
|
48 |
|
|
; Embedded Multiplier 9-bit elements ; 0 / 160 ( 0 % ) ;
|
49 |
|
|
; Total GXB Receiver Channel PCS ; 0 / 4 ( 0 % ) ;
|
50 |
|
|
; Total GXB Receiver Channel PMA ; 0 / 4 ( 0 % ) ;
|
51 |
|
|
; Total GXB Transmitter Channel PCS ; 0 / 4 ( 0 % ) ;
|
52 |
|
|
; Total GXB Transmitter Channel PMA ; 0 / 4 ( 0 % ) ;
|
53 |
|
|
; Total PLLs ; 0 / 6 ( 0 % ) ;
|
54 |
|
|
; Device ; EP4CGX30CF23C6 ;
|
55 |
|
|
; Timing Models ; Final ;
|
56 |
|
|
+------------------------------------+-----------------------------------------------+
|
57 |
|
|
|
58 |
|
|
|