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-- ------------------------------------------------------------------------

-- Copyright (C) 2005 Arif Endro Nugroho

-- All rights reserved.

-- 

-- Redistribution and use in source and binary forms, with or without

-- modification, are permitted provided that the following conditions

-- are met:

-- 

-- 1. Redistributions of source code must retain the above copyright

--    notice, this list of conditions and the following disclaimer.

-- 2. Redistributions in binary form must reproduce the above copyright

--    notice, this list of conditions and the following disclaimer in the

--    documentation and/or other materials provided with the distribution.

-- 

-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS

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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY

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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

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-- End Of License.

-- ------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity counter2bit is

   port (

      clock : in  std_logic;

      clear : in  std_logic;

      count : out std_logic_vector (1 downto 0)

      );

end counter2bit;

architecture data_flow of counter2bit is

signal tmp : std_logic_vector (1 downto 0) := ( B"00" );

begin

   process (clock, clear)

   begin

      if (clear = '1') then

         tmp <= "00";

      elsif (clock = '1' and clock'event) then

         tmp <= tmp + 1;

      end if;

   end process;

   count <= tmp;

end data_flow;