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[/] [mini_aes/] [trunk/] [source/] [io_interface.vhdl] - Blame information for rev 22

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1 21 arif_endro 
-- ------------------------------------------------------------------------
2 15 arif_endro 
-- Copyright (C) 2005 Arif Endro Nugroho
3 21 arif_endro 
-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- 1. Redistributions of source code must retain the above copyright
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--    notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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--    notice, this list of conditions and the following disclaimer in the
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--    documentation and/or other materials provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- End Of License.
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-- ------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity io_interface is
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   port (
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      clock      : in  std_logic;
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      clear      : in  std_logic;
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      load_i     : in  std_logic;
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      load_i_int : out std_logic;
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      data_i     : in  std_logic_vector (7 downto 0);
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      key_i      : in  std_logic_vector (7 downto 0);
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      data_o     : out std_logic_vector (7 downto 0);
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      data_o_int : in  std_logic_vector (127 downto 000);
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      data_i_int : out std_logic_vector (127 downto 000);
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      key_i_int  : out std_logic_vector (127 downto 000);
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      done_o_int : in  std_logic;
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      done_o     : out std_logic
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      );
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end io_interface;
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architecture data_flow of io_interface is
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type fifo16x8 is array ( 0 to 15 ) of std_logic_vector (7 downto 0);
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signal fifo_data : fifo16x8 :=
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(
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 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000"
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);
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signal fifo_key : fifo16x8 :=
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(
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 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000"
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);
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signal fifo_output : fifo16x8 :=
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(
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 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000"
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);
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signal load_core   : std_logic := '0';
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signal done_int    : std_logic := '0';
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signal up_counter  : integer range 0 to 15 := 0;
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-- signal data_o_int : std_logic_vector (127 downto 000) :=
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--   ( X"3925841D_02DC09FB_DC118597_196A0B32" );  -- CT 0
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begin
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load_i_int <= load_core;
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process(clock, clear)
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begin
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if (clear = '1') then
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   done_o <= '0';
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elsif (clock = '1' and clock'event) then
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   done_o <= done_int;
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end if;
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end process;
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process(clock, clear)
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begin
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if (clear = '1') then
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   up_counter <= 0;
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elsif (clock = '1' and clock'event) then
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   if (done_o_int = '1') then
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      up_counter <= 0;
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-- elsif ((up_counter = 0) and (done_o_int = '1')) then
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-- elsif (done_o_int = '0' and done_o_int'event) then
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-- 20051219 FIXME
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      done_int   <= '1';
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   elsif (up_counter < 15 ) then
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      up_counter <= up_counter + 1;
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   else
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--    up_counter <= 0;
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      done_int   <= '0';
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   end if;
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end if;
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end process;
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process(clock, clear)
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begin
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if (clear = '1') then
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   fifo_output <= (others => (others => '0'));
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elsif (clock = '1' and clock'event) then
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   if (done_o_int = '1') then
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      fifo_output <= ( data_o_int (127 downto 120), data_o_int (119 downto 112), data_o_int (111 downto 104),
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                       data_o_int (103 downto 096), data_o_int (095 downto 088), data_o_int (087 downto 080),
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                       data_o_int (079 downto 072), data_o_int (071 downto 064), data_o_int (063 downto 056),
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                       data_o_int (055 downto 048), data_o_int (047 downto 040), data_o_int (039 downto 032),
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                       data_o_int (031 downto 024), data_o_int (023 downto 016), data_o_int (015 downto 008),
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                       data_o_int (007 downto 000));
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   end if;
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end if;
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end process;
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process(clock, clear)
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begin
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if (clear = '1') then
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data_o <= (others => '0');
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elsif (clock = '1' and clock'event) then
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data_o <= fifo_output(up_counter);
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end if;
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end process;
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process(clock, clear)
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begin
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   if (clear = '1') then
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      fifo_key     <= (others => (others => '0'));
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      fifo_data    <= (others => (others => '0'));
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      load_core    <= '1';
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   elsif (clock = '1' and clock'event) then
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      if (load_i  = '1') then
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         fifo_key     <= (fifo_key (1 to 15) & key_i);
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         fifo_data    <= (fifo_data (1 to 15) & data_i);
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      end if;
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         load_core    <= load_i;
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   end if;
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end process;
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key_i_int<= ( fifo_key (00) & fifo_key (01) & fifo_key (02) & fifo_key (03) &
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              fifo_key (04) & fifo_key (05) & fifo_key (06) & fifo_key (07) &
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              fifo_key (08) & fifo_key (09) & fifo_key (10) & fifo_key (11) &
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              fifo_key (12) & fifo_key (13) & fifo_key (14) & fifo_key (15) );
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data_i_int<= ( fifo_data (00) & fifo_data (01) & fifo_data (02) & fifo_data (03) &
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               fifo_data (04) & fifo_data (05) & fifo_data (06) & fifo_data (07) &
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               fifo_data (08) & fifo_data (09) & fifo_data (10) & fifo_data (11) &
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               fifo_data (12) & fifo_data (13) & fifo_data (14) & fifo_data (15) );
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end data_flow;

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