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mcafruni |
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-- --
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-- --
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-- miniMIPS Superscalar Processor : Address calculation stage --
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-- based on miniMIPS Processor --
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-- --
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-- --
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-- Author : Miguel Cafruni --
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-- miguel_cafruni@hotmail.com --
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-- December 2018 --
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.pack_mips.all;
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entity pps_pf is
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port (
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clock : in bus1;
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clock2 : in bus1;
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reset : in bus1;
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stop_all : in bus1; -- Unconditionnal locking of the pipeline stage
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stop_all2 : in bus1;
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-- Asynchronous inputs
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bra_cmd : in bus1; -- Branch
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bra_adr : in bus32; -- Address to load when an effective branch
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exch_cmd : in bus1; -- Exception branch
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exch_adr : in bus32; -- Exception vector
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-- Asynchronous inputs 2
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bra_cmd2 : in bus1; -- Branch
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bra_adr2 : in bus32; -- Address to load when an effective branch
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exch_cmd2 : in bus1; -- Exception branch
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exch_adr2 : in bus32; -- Exception vector
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stop_pf : in bus1; -- Lock the stage
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stop_pf2 : in bus1; -- Lock the stage
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-- Synchronous output to EI stage
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PF_pc : out bus32; -- PC value
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PF_pc_4 : out bus32 -- PC+4 value
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);
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end pps_pf;
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architecture rtl of pps_pf is
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signal suivant : bus32; -- Preparation of the future pc
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signal suivant4 : bus32; -- Preparation of the future pc
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signal pc_interne : bus32; -- Value of the pc output, needed for an internal reading
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signal pc_interne4 : bus32; -- Value of the pc output, needed for an internal reading
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signal lock : bus1; -- Specify the authorization of the pc evolution
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signal lock2 : bus1; -- independente para o pipe 2, 06.02.18
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begin
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-- Connexion the pc to the internal pc
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PF_pc <= pc_interne;
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PF_pc_4 <= pc_interne4;
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-- Elaboration of an potential future pc
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suivant <= exch_adr when exch_cmd = '1' else
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bra_adr when bra_cmd = '1' else
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bus32(unsigned(pc_interne) + 8);
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suivant4 <= bus32(unsigned(exch_adr2) + 4) when exch_cmd2 = '1' else
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bra_adr2 when bra_cmd2 = '1' else
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bus32(unsigned(pc_interne4) + 8);
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lock <= '1' when stop_all = '1' else -- Lock this stage when all the pipeline is locked
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'0' when exch_cmd = '1' else -- Exception
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'0' when bra_cmd = '1' else -- Branch
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'1' when stop_pf = '1' else -- Wait for the branch hazard
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'0'; -- Normal evolution
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lock2 <= '1' when stop_all2 = '1' else -- Lock this stage when all the pipeline is locked
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'0' when exch_cmd2 = '1' else -- Exception
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'0' when bra_cmd2 = '1' else -- Branch
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'1' when stop_pf2 = '1' else -- Wait for the branch hazard
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'0'; -- Normal evolution
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-- Synchronous evolution of the pc
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process(clock)
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begin
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if rising_edge(clock) then
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if reset='1' then
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-- PC reinitialisation with the boot address
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pc_interne <= ADR_INIT;
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elsif lock='0' then
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-- PC not locked
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pc_interne <= suivant;
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end if;
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end if;
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end process;
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process(clock2)
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begin
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if falling_edge(clock2) then
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if reset='1' then
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-- PC reinitialisation with the boot address
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pc_interne4 <= ADR_INIT4;
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elsif (lock2='0') then
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-- PC not locked
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pc_interne4 <= suivant4;
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end if;
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end if;
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end process;
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end rtl;
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