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mcafruni |
------------------------------------------------------------------------------------
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-- --
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-- Copyright (c) 2004, Hangouet Samuel --
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-- , Jan Sebastien --
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-- , Mouton Louis-Marie --
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-- , Schneider Olivier all rights reserved --
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-- --
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-- This file is part of miniMIPS. --
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-- --
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-- miniMIPS is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation; either version 2 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- miniMIPS is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with miniMIPS; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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------------------------------------------------------------------------------------
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-- If you encountered any problem, please contact :
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--
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-- lmouton@enserg.fr
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-- oschneid@enserg.fr
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-- shangoue@enserg.fr
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--
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--------------------------------------------------------------------------
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-- --
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-- --
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-- miniMIPS Processor : Arithmetical and logical unit --
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-- --
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-- --
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-- --
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-- Authors : Hangouet Samuel --
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-- Jan Sébastien --
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-- Mouton Louis-Marie --
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-- Schneider Olivier --
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-- --
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-- june 2003 --
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.pack_mips.all;
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entity alu2 is
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port
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(
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clock : in bus1;
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reset : in bus1;
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op1 : in bus32; -- Operand 1
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op2 : in bus32; -- Operand 2
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ctrl : in alu_ctrl_type; -- Opearator control
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hilo_p1 : in bus64;
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hilo_p2p1 : out bus64;
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res : out bus32; -- The result is 32 bit long
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overflow : out bus1 -- Overflow of the result
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);
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end alu2;
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architecture rtl of alu2 is
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-- Signals to pre-process the operands
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signal efct_op1, efct_op2 : bus33; -- Effective operands of the adder (33 bits)
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signal comp_op2 : bus1; -- Select the opposite of operand 2
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signal igno_op2 : bus1; -- Ignore op 2 (put zeros)
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signal sign_op1 : bus1; -- High bit of op 1
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signal sign_op2 : bus1; -- High bit of op 2
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signal signe : bus1; -- Signed operation (bit sign extension)
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signal shift_val : natural range 0 to 31; -- Value of the shift
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-- Signals for internal results
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signal res_shl, res_shr : bus32; -- Results of left and right shifter
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signal res_lui : bus32; -- Result of Load Upper Immediate
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signal res_add : bus33; -- Result of the adder
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signal res_mul : std_logic_vector(31 downto 0); -- Resultado da multiplicacao 25.05.18
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signal carry : bus33; -- Carry for the adder
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signal nul : bus1; -- Check if the adder result is zero
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signal hilo : bus64; -- Internal registers to store the multiplication operation
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signal tmp_hilo : bus64; -- Internal registers to store the multiplication operation (synchronised)
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signal hilop1 : bus64;
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signal i_mult : bus1;
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begin
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-- Process if the operation is signed compliant
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signe <= '1' when (ctrl=OP_ADD or ctrl=OP_SUB or ctrl=OP_SLT or ctrl=OP_SNEG or ctrl=OP_SPOS or ctrl=OP_LNEG or ctrl=OP_LPOS)
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else
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'0';
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sign_op1 <= signe and op1(31);
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sign_op2 <= signe and op2(31);
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-- Selection of the value of the second operand : op2 or -op2 (ie not op2 + 1)
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comp_op2 <= '1' when -- The opposite of op2 is used
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(ctrl=OP_SUB or ctrl=OP_SUBU) -- Opposite of the operand 2 to obtain a substraction
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or (ctrl=OP_SLT or ctrl=OP_SLTU) -- Process the difference to check the lesser than operation for the operands
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or (ctrl=OP_EQU or ctrl=OP_NEQU) -- Process the difference to check the equality of the operands
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else
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'0'; -- by default, op2 is used
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igno_op2 <= '1' when -- Op 2 will be zero (when comp_op2='0')
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(ctrl=OP_SPOS or ctrl=OP_LNEG) -- Process if the op1 is nul with op1+0
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else
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'0';
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-- Effective signals for the adder
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efct_op2 <= not (sign_op2 & op2) when (comp_op2='1') else -- We take the opposite of op2 to get -op2 (we will add 1 with the carry)
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(others => '0') when (igno_op2='1') else -- Op2 is zero
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(sign_op2 & op2); -- by default we use op2 (33 bits long)
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efct_op1 <= sign_op1 & op1;
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-- Execution of the addition
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carry <= X"00000000" & comp_op2; -- Carry to one when -op2 is needed
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res_add <= std_logic_vector(unsigned(efct_op1) + unsigned(efct_op2) + unsigned(carry));
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res_mul <= std_logic_vector(signed(efct_op1(15 downto 0))*signed(efct_op2(15 downto 0)));
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nul <= '1' when (res_add(31 downto 0)=X"00000000") else '0'; -- Check the nullity of the result (se os registradores contiverem o mesmo valor o resultado é 1)
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-- Value of the shift for the programmable shifter
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shift_val <= to_integer(unsigned(op1(4 downto 0)));
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res_shl <= bus32(shift_left(unsigned(op2), shift_val));
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res_shr <= not bus32(shift_right(unsigned(not op2) , shift_val)) when (ctrl=OP_SRA and op2(31)='1') else
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bus32(shift_right(unsigned(op2), shift_val));
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res_lui <= op2(15 downto 0) & X"0000";
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-- Affectation of the hilo register if necessary
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tmp_hilo <= std_logic_vector(signed(op1)*signed(op2)) when (ctrl=OP_MULT) else
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std_logic_vector(unsigned(op1)*unsigned(op2)) when (ctrl=OP_MULTU) else
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op1 & hilo(31 downto 0) when (ctrl=OP_MTHI) else
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hilo(63 downto 32) & op1 when (ctrl=OP_MTLO) else
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(others => '0');
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hilo_p2p1 <= tmp_hilo;
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-- Check the overflows
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overflow <= '1' when ((ctrl=OP_ADD and op1(31)=efct_op2(31) and op1(31)/=res_add(31))
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or (ctrl=OP_SUB and op1(31)/=op2(31) and op1(31)/=res_add(31))) else
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'0'; -- Only ADD and SUB can overflow
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-- Result affectation
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res <=
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-- Arithmetical operations
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res_add(31 downto 0) when (ctrl=OP_ADD or ctrl=OP_ADDU or ctrl=OP_SUB or ctrl=OP_SUBU) else
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res_mul(31 downto 0) when (ctrl=OP_MULT2) else
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-- Logical operations
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op1 and op2 when (ctrl=OP_AND) else
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op1 or op2 when (ctrl=OP_OR) else
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op1 nor op2 when (ctrl=OP_NOR) else
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op1 xor op2 when (ctrl=OP_XOR) else
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-- Different tests : the result is one when the test is succesful
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(0 => res_add(32), others=>'0') when (ctrl=OP_SLTU or ctrl=OP_SLT) else
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(0 => nul, others=>'0') when (ctrl=OP_EQU) else
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(0 => not nul, others=>'0') when (ctrl=OP_NEQU) else -- inverte o sinal nul, se nao sao iguais os valores dos registradores, entao o branch sera tomado
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(0 => op1(31), others=>'0') when (ctrl=OP_SNEG) else
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(0 => not (op1(31) or nul), others=>'0') when (ctrl=OP_SPOS) else
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(0 => (op1(31) or nul), others=>'0') when (ctrl=OP_LNEG) else
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(0 => not op1(31), others=>'0') when (ctrl=OP_LPOS) else
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-- Shifts
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res_shl when (ctrl=OP_SLL) else
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res_shr when (ctrl=OP_SRL or ctrl=OP_SRA) else
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res_lui when (ctrl=OP_LUI) else
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-- Internal registers
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hilo(63 downto 32) when (ctrl=OP_MFHI and i_mult='1') else
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hilo(31 downto 0) when ((ctrl=OP_MFLO or ctrl=OP_MULT or ctrl=OP_MULTU) and i_mult='1') else
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hilop1(63 downto 32) when (ctrl=OP_MFHI and i_mult='0') else
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hilop1(31 downto 0) when (ctrl=OP_MFLO and i_mult='0') else -- veio do pipe 1 20-12-2018 or ctrl=OP_MULT or ctrl=OP_MULTU
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op1 when (ctrl=OP_MTHI or ctrl=OP_MTLO) else
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op2 when (ctrl=OP_OP2) else
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-- Always true
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X"00000001" when (ctrl=OP_OUI) else -- J (jump)
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-- Unknown operation or nul result desired
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(others => '0');
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-- Save the hilo register
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process (clock)
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begin
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if rising_edge(clock) then
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if reset = '1' then
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hilo <= (others => '0');
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i_mult <= '0';
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elsif (ctrl = OP_MULT) or (ctrl = OP_MULTU) or (ctrl = OP_MTLO) or (ctrl = OP_MTHI) then
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hilo <= tmp_hilo;
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i_mult <= '1';
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else
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i_mult <= '0';
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end if;
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end if;
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end process;
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process (hilo_p1)
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begin
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hilop1 <= hilo_p1; -- salva entrada assincrona do resultado da multiplicacao feita no pipe 1 20-12-2018
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end process;
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end rtl;
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