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------------------------------------------------------------------------------------
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-- --
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-- Copyright (c) 2004, Hangouet Samuel --
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-- , Jan Sebastien --
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-- , Mouton Louis-Marie --
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-- , Schneider Olivier all rights reserved --
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-- --
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-- This file is part of miniMIPS. --
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-- --
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-- miniMIPS is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation; either version 2 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- miniMIPS is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with miniMIPS; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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------------------------------------------------------------------------------------
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-- If you encountered any problem, please contact :
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--
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-- lmouton@enserg.fr
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-- oschneid@enserg.fr
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-- shangoue@enserg.fr
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--
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--------------------------------------------------------------------------
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-- --
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-- --
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-- miniMIPS Processor : bus controler --
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-- --
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-- --
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-- --
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-- Authors : Hangouet Samuel --
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-- Jan Sébastien --
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-- Mouton Louis-Marie --
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-- Schneider Olivier --
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-- --
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-- june 2003 --
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--------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.pack_mips.all;
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entity bus_ctrl01 is
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port
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(
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clock : std_logic;
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reset : std_logic;
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-- Interruption in the pipeline
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interrupt : in std_logic;
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-- Interface for the Instruction Extraction Stage
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adr_from_ei : in bus32; -- The address of the data to read
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instr_to_ei : out bus32; -- Instruction from the memory
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-- Interface with the MEMory Stage
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req_from_mem : in std_logic; -- Request to access the ram
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r_w_from_mem : in std_logic; -- Read/Write request
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adr_from_mem : in bus32; -- Address in ram
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data_from_mem : in bus32; -- Data to write in ram
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data_to_mem : out bus32; -- Data from the ram to the MEMory stage
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-- RAM interface signals
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req_to_ram : out std_logic; -- Request to ram
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adr_to_ram : out bus32; -- Address of the data to read or write
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r_w_to_ram : out std_logic; -- Read/Write request
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ack_from_ram : in std_logic; -- Acknowledge from the memory
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data_inout_ram : inout bus32; -- Data from/to the memory
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-- Pipeline progress control signal
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stop_all : out std_logic
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);
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end bus_ctrl01;
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architecture rtl of bus_ctrl01 is
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type ctrl_state is ( ST1, ST2 );
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signal cs, ns : ctrl_state;
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signal ei_buffer : bus32; -- Buffer storing the data for EI
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signal r_w : std_logic; -- Current utilisation of the tristate bus
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signal data_in : bus32; -- Data read on the tristate bus
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signal req_allowed : std_logic;
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begin
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-- Read/write on the tristate bus
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process (r_w, data_from_mem, data_inout_ram)
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begin
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r_w_to_ram <= r_w;
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if r_w='0' then -- Reads bus
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data_inout_ram <= (others => 'Z');
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data_in <= data_inout_ram;
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else -- Writing of the data from the MEM stage
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data_inout_ram <= data_from_mem;
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data_in <= (others => '0');
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end if;
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end process;
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process (clock)
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begin
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if rising_edge(clock) then
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if reset='1' then
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cs <= ST1;
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ei_buffer <= (others => '0');
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else
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if cs=ST1 then
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-- Storing of the data to send to EI stage
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ei_buffer <= data_in;
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end if;
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cs <= ns;
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end if;
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end if;
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end process;
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process (clock, ack_from_ram)
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begin
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if ack_from_ram = '0' then
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req_allowed <= '0'; -- bloqueia nova requisicao
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elsif rising_edge(clock) then
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if ack_from_ram = '1' then
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req_allowed <= '1'; -- libera nova requisicao
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end if;
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end if;
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end process;
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process (req_allowed, ack_from_ram)
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begin
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if req_allowed = '1' then
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req_to_ram <= '1'; -- nova requisicao
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elsif ack_from_ram = '0' then
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req_to_ram <= '1'; -- nova requisicao
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else
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req_to_ram <= '0'; -- sem requisicao
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end if;
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end process;
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process (cs, interrupt, adr_from_ei, req_from_mem, r_w_from_mem, adr_from_mem, ack_from_ram)
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begin
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if interrupt = '1' then -- An interruption is detected
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ns <= ST1; -- Get back to the reading request
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stop_all <= '0'; -- The pipeline is unlock for taking in account the interruption
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adr_to_ram <= adr_from_ei;
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r_w <= '0';
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else
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case cs is
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when ST1 => -- First step the reading for EI
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adr_to_ram <= adr_from_ei;
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r_w <= '0';
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if ack_from_ram='1' then
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if req_from_mem='1' then
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-- If request from MEM, then step 2
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ns <= ST2;
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stop_all <= '1';
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else
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-- else next reading for EI
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ns <= ST1;
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stop_all <= '0';
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end if;
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else
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-- Wait the end of the reading
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ns <= ST1;
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stop_all <= '1';
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end if;
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when ST2 => -- Treat the request from the MEM stage
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adr_to_ram <= adr_from_mem;
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r_w <= r_w_from_mem;
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-- Wait the acknowledge from the RAM
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if ack_from_ram='1' then
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ns <= ST1;
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stop_all <= '0';
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else
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ns <= ST2;
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stop_all <= '1';
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end if;
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end case;
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end if;
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end process;
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data_to_mem <= data_in;
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instr_to_ei <= ei_buffer when cs=ST2 else data_in;
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end rtl;
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