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mcafruni |
------------------------------------------------------------------------------------
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-- --
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-- Copyright (c) 2004, Hangouet Samuel --
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-- , Jan Sebastien --
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-- , Mouton Louis-Marie --
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-- , Schneider Olivier all rights reserved --
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-- --
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-- This file is part of miniMIPS. --
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-- --
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-- miniMIPS is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation; either version 2 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- miniMIPS is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with miniMIPS; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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------------------------------------------------------------------------------------
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-- If you encountered any problem, please contact :
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--
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-- lmouton@enserg.fr
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-- oschneid@enserg.fr
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-- shangoue@enserg.fr
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--
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--------------------------------------------------------------------------
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-- --
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-- --
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-- miniMIPS Processor : Instruction extraction stage --
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-- --
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-- --
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-- --
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-- Authors : Hangouet Samuel --
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-- Jan Sébastien --
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-- Mouton Louis-Marie --
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-- Schneider Olivier --
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-- --
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-- june 2003 --
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.pack_mips.all;
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entity pps_ei_2 is
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port (
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clock : in std_logic;
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reset : in std_logic;
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clear : in std_logic; -- Clear the pipeline stage
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stop_all2 : in std_logic; -- Evolution locking signal
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-- Asynchronous inputs
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stop_ei : in std_logic; -- Lock the EI_adr and Ei_instr registers
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genop : in std_logic; -- Send nops
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-- Bus controler interface
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CTE_instr : in bus32; -- Instruction from the memory
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ETC_adr : out bus32; -- Address to read in memory
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-- Synchronous inputs from PF stage
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PF_pc : in bus32; -- Current value of the pc (desnecessario no EI2)
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-- Synchronous outputs to DI stage
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EI_instr : out bus32; -- Read interface
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EI_adr : out bus32; -- Address from the read instruction
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EI_it_ok : out std_logic -- Allow hardware interruptions
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);
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end pps_ei_2;
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architecture rtl of pps_ei_2 is
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begin
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ETC_adr <= PF_pc; -- Connexion of the PC to the memory address bus
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-- Set the results
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process (clock)
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begin
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if rising_edge(clock) then
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if reset='1' then
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EI_instr <= INS_NOP;
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EI_adr <= (others => '0');
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EI_it_ok <= '0';
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elsif stop_all2='0' then
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if clear='1' then
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-- Clear the stage
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EI_instr <= INS_NOP;
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EI_it_ok <= '0';
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elsif genop='1' and stop_ei='0' then
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-- Send a nop
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EI_instr <= INS_NOP;
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EI_it_ok <= '1';
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elsif stop_ei='0' then
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-- Normal evolution
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EI_adr <= PF_pc;
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EI_instr <= CTE_instr;
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EI_it_ok <= '1';
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end if;
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end if;
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end if;
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end process;
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end rtl;
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