| 1 |
21 |
mcafruni |
------------------------------------------------------------------------------------
|
| 2 |
|
|
-- --
|
| 3 |
|
|
-- Copyright (c) 2004, Hangouet Samuel --
|
| 4 |
|
|
-- , Jan Sebastien --
|
| 5 |
|
|
-- , Mouton Louis-Marie --
|
| 6 |
|
|
-- , Schneider Olivier all rights reserved --
|
| 7 |
|
|
-- --
|
| 8 |
|
|
-- This file is part of miniMIPS. --
|
| 9 |
|
|
-- --
|
| 10 |
|
|
-- miniMIPS is free software; you can redistribute it and/or modify --
|
| 11 |
|
|
-- it under the terms of the GNU General Public License as published by --
|
| 12 |
|
|
-- the Free Software Foundation; either version 2 of the License, or --
|
| 13 |
|
|
-- (at your option) any later version. --
|
| 14 |
|
|
-- --
|
| 15 |
|
|
-- miniMIPS is distributed in the hope that it will be useful, --
|
| 16 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
|
| 17 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
|
| 18 |
|
|
-- GNU General Public License for more details. --
|
| 19 |
|
|
-- --
|
| 20 |
|
|
-- You should have received a copy of the GNU General Public License --
|
| 21 |
|
|
-- along with miniMIPS; if not, write to the Free Software --
|
| 22 |
|
|
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
|
| 23 |
|
|
-- --
|
| 24 |
|
|
------------------------------------------------------------------------------------
|
| 25 |
|
|
|
| 26 |
|
|
|
| 27 |
|
|
-- If you encountered any problem, please contact :
|
| 28 |
|
|
--
|
| 29 |
|
|
-- lmouton@enserg.fr
|
| 30 |
|
|
-- oschneid@enserg.fr
|
| 31 |
|
|
-- shangoue@enserg.fr
|
| 32 |
|
|
--
|
| 33 |
|
|
|
| 34 |
|
|
|
| 35 |
|
|
|
| 36 |
|
|
--------------------------------------------------------------------------
|
| 37 |
|
|
-- --
|
| 38 |
|
|
-- --
|
| 39 |
|
|
-- Processor miniMIPS : Execution stage --
|
| 40 |
|
|
-- --
|
| 41 |
|
|
-- --
|
| 42 |
|
|
-- --
|
| 43 |
|
|
-- Authors : Hangouet Samuel --
|
| 44 |
|
|
-- Jan Sébastien --
|
| 45 |
|
|
-- Mouton Louis-Marie --
|
| 46 |
|
|
-- Schneider Olivier --
|
| 47 |
|
|
-- --
|
| 48 |
|
|
-- june 2003 --
|
| 49 |
|
|
--------------------------------------------------------------------------
|
| 50 |
|
|
|
| 51 |
|
|
library IEEE;
|
| 52 |
|
|
use IEEE.std_logic_1164.all;
|
| 53 |
|
|
use IEEE.numeric_std.all;
|
| 54 |
|
|
|
| 55 |
|
|
library work;
|
| 56 |
|
|
use work.pack_mips.all;
|
| 57 |
|
|
use work.alu;
|
| 58 |
|
|
|
| 59 |
|
|
entity pps_ex is
|
| 60 |
|
|
port(
|
| 61 |
|
|
clock : in std_logic;
|
| 62 |
|
|
clock2 : in std_logic;
|
| 63 |
|
|
reset : in std_logic;
|
| 64 |
|
|
stop_all : in std_logic; -- Unconditionnal locking of outputs
|
| 65 |
|
|
stop_all2 : in std_logic; -- 07-08-2018
|
| 66 |
|
|
clear : in std_logic; -- Clear the pipeline stage
|
| 67 |
|
|
|
| 68 |
|
|
-- Datas from DI stage
|
| 69 |
|
|
DI_bra : in std_logic; -- Branch instruction
|
| 70 |
|
|
DI_link : in std_logic; -- Branch with link
|
| 71 |
|
|
DI_op1 : in bus32; -- Operand 1 for alu
|
| 72 |
|
|
DI_op2 : in bus32; -- Operand 2 for alu
|
| 73 |
|
|
DI_code_ual : in alu_ctrl_type; -- Alu operation
|
| 74 |
|
|
DI_offset : in bus32; -- Offset for address calculation
|
| 75 |
|
|
DI_adr_reg_dest : in adr_reg_type; -- Destination register address for the result
|
| 76 |
|
|
DI_ecr_reg : in std_logic; -- Effective writing of the result
|
| 77 |
|
|
DI_mode : in std_logic; -- Address mode (relative to pc ou index by a register)
|
| 78 |
|
|
DI_op_mem : in std_logic; -- Memory operation
|
| 79 |
|
|
DI_r_w : in std_logic; -- Type of memory operation (read or write)
|
| 80 |
|
|
DI_adr : in bus32; -- Instruction address
|
| 81 |
|
|
DI_exc_cause : in bus32; -- Potential cause exception
|
| 82 |
|
|
DI_level : in level_type; -- Availability stage of the result for bypassing
|
| 83 |
|
|
DI_it_ok : in std_logic; -- Allow hardware interruptions
|
| 84 |
|
|
|
| 85 |
|
|
|
| 86 |
|
|
EX2_data_hilo : in bus64;--resultado da multiplicacao do pieline2
|
| 87 |
|
|
EX_data_hilo : out bus64;
|
| 88 |
|
|
-- Synchronous outputs to MEM stage
|
| 89 |
|
|
EX_adr : out bus32; -- Instruction address
|
| 90 |
|
|
EX_bra_confirm : out std_logic; -- Branch execution confirmation
|
| 91 |
|
|
EX_data_ual : out bus32; -- Ual result
|
| 92 |
|
|
EX_adresse : out bus32; -- Address calculation result
|
| 93 |
|
|
EX_adresse_p1p2 : out bus32; -- resultado do calculo do endereco do desvio + 4 para pipe 2
|
| 94 |
|
|
EX_adr_reg_dest : out adr_reg_type; -- Destination register for the result
|
| 95 |
|
|
EX_ecr_reg : out std_logic; -- Effective writing of the result
|
| 96 |
|
|
EX_op_mem : out std_logic; -- Memory operation needed
|
| 97 |
|
|
EX_r_w : out std_logic; -- Type of memory operation (read or write)
|
| 98 |
|
|
EX_exc_cause : out bus32; -- Potential cause exception
|
| 99 |
|
|
EX_level : out level_type; -- Availability stage of result for bypassing
|
| 100 |
|
|
EX_it_ok : out std_logic -- Allow hardware interruptions
|
| 101 |
|
|
);
|
| 102 |
|
|
end entity;
|
| 103 |
|
|
|
| 104 |
|
|
|
| 105 |
|
|
architecture rtl of pps_ex is
|
| 106 |
|
|
|
| 107 |
|
|
component alu
|
| 108 |
|
|
port (
|
| 109 |
|
|
clock : in bus1;
|
| 110 |
|
|
reset : in bus1;
|
| 111 |
|
|
op1 : in bus32; -- Operand 1
|
| 112 |
|
|
op2 : in bus32; -- Operand 2
|
| 113 |
|
|
ctrl : in alu_ctrl_type; -- Operation
|
| 114 |
|
|
hilo_p2 : in bus64;
|
| 115 |
|
|
hilo_p1p2 : out bus64;
|
| 116 |
|
|
res : out bus32; -- Result
|
| 117 |
|
|
overflow : out bus1 -- Overflow
|
| 118 |
|
|
);
|
| 119 |
|
|
end component;
|
| 120 |
|
|
|
| 121 |
|
|
signal res_ual : bus32; -- Alu result output
|
| 122 |
|
|
signal base_adr : bus32; -- Output of the address mode mux selection
|
| 123 |
|
|
|
| 124 |
|
|
signal pre_ecr_reg : std_logic; -- Output of mux selection for writing command to register
|
| 125 |
|
|
signal pre_data_ual : bus32; -- Mux selection of the data to write
|
| 126 |
|
|
signal pre_bra_confirm : std_logic; -- Result of the test in alu when branch instruction
|
| 127 |
|
|
signal pre_exc_cause : bus32; -- Preparation of the exception detection signal
|
| 128 |
|
|
signal overflow_ual : std_logic; -- Dectection of the alu overflow
|
| 129 |
|
|
signal ex_address_p1p2 : bus32;
|
| 130 |
|
|
signal hilo_p1p2_s : bus64;
|
| 131 |
|
|
begin
|
| 132 |
|
|
|
| 133 |
|
|
-- Alu instantiation
|
| 134 |
|
|
U1_alu : alu port map (clock => clock, reset => reset, op1=>DI_op1, op2=>DI_op2, ctrl=>DI_code_ual,
|
| 135 |
|
|
res=>res_ual, overflow=>overflow_ual, hilo_p2=>EX2_data_hilo, hilo_p1p2=>hilo_p1p2_s);
|
| 136 |
|
|
|
| 137 |
|
|
-- Calculation of the future outputs
|
| 138 |
|
|
base_adr <= DI_op1 when DI_mode='0' else DI_adr; -- *** base_adr = DI_op1 = 0 na instrucao JAL ***
|
| 139 |
|
|
pre_ecr_reg <= DI_ecr_reg when DI_link='0' else pre_bra_confirm;
|
| 140 |
|
|
pre_data_ual <= res_ual when DI_link='0' else bus32(unsigned(DI_adr) + 8); --***Endereco de retorno (link address) gravado pela instrucao JAL no registrador D_31, que depois sera usado pela intrucao de retorno da rotina, JR.***
|
| 141 |
|
|
pre_bra_confirm <= DI_bra and res_ual(0);
|
| 142 |
|
|
pre_exc_cause <= DI_exc_cause when DI_exc_cause/=IT_NOEXC else
|
| 143 |
|
|
IT_OVERF when overflow_ual='1' else
|
| 144 |
|
|
IT_NOEXC;
|
| 145 |
|
|
|
| 146 |
|
|
-- Set the synchronous outputs
|
| 147 |
|
|
process(clock)
|
| 148 |
|
|
begin
|
| 149 |
|
|
if rising_edge(clock) then
|
| 150 |
|
|
if reset='1' then
|
| 151 |
|
|
EX_adr <= (others => '0');
|
| 152 |
|
|
EX_bra_confirm <= '0';
|
| 153 |
|
|
EX_data_ual <= (others => '0');
|
| 154 |
|
|
EX_adresse <= (others => '0');
|
| 155 |
|
|
EX_adr_reg_dest <= (others => '0');
|
| 156 |
|
|
EX_ecr_reg <= '0';
|
| 157 |
|
|
EX_op_mem <= '0';
|
| 158 |
|
|
EX_r_w <= '0';
|
| 159 |
|
|
EX_exc_cause <= IT_NOEXC;
|
| 160 |
|
|
EX_level <= LVL_DI;
|
| 161 |
|
|
EX_it_ok <= '0';
|
| 162 |
|
|
elsif stop_all = '0' then
|
| 163 |
|
|
if clear = '1' then -- Clear the stage
|
| 164 |
|
|
EX_adr <= DI_adr;
|
| 165 |
|
|
EX_bra_confirm <= '0';
|
| 166 |
|
|
EX_data_ual <= (others => '0');
|
| 167 |
|
|
EX_adresse <= (others => '0');
|
| 168 |
|
|
EX_adr_reg_dest <= (others => '0');
|
| 169 |
|
|
EX_ecr_reg <= '0';
|
| 170 |
|
|
EX_op_mem <= '0';
|
| 171 |
|
|
EX_r_w <= '0';
|
| 172 |
|
|
EX_exc_cause <= IT_NOEXC;
|
| 173 |
|
|
EX_level <= LVL_DI;
|
| 174 |
|
|
EX_it_ok <= '0';
|
| 175 |
|
|
else -- Normal evolution
|
| 176 |
|
|
EX_adr <= DI_adr;
|
| 177 |
|
|
EX_bra_confirm <= pre_bra_confirm;
|
| 178 |
|
|
EX_data_ual <= pre_data_ual;
|
| 179 |
|
|
EX_adr_reg_dest <= DI_adr_reg_dest;
|
| 180 |
|
|
EX_ecr_reg <= pre_ecr_reg;
|
| 181 |
|
|
EX_op_mem <= DI_op_mem;
|
| 182 |
|
|
EX_r_w <= DI_r_w;
|
| 183 |
|
|
EX_exc_cause <= pre_exc_cause;
|
| 184 |
|
|
EX_level <= DI_level;
|
| 185 |
|
|
EX_it_ok <= DI_it_ok;
|
| 186 |
|
|
EX_adresse <= bus32(unsigned(DI_offset) + unsigned(base_adr)); --*** base_adr = DI_op1 = 0 na instrucao JAL, para calcular o endereco alvo ***
|
| 187 |
|
|
ex_address_p1p2 <= bus32(unsigned(DI_offset) + unsigned(base_adr));
|
| 188 |
|
|
end if; -- fim if clear = '1'
|
| 189 |
|
|
end if; -- fim if stop_all = '0'
|
| 190 |
|
|
end if; -- fim if rising_edge(clock)
|
| 191 |
|
|
end process;
|
| 192 |
|
|
|
| 193 |
|
|
process(clock2)
|
| 194 |
|
|
begin
|
| 195 |
|
|
if rising_edge(clock2) then
|
| 196 |
|
|
if reset = '1' then
|
| 197 |
|
|
EX_adresse_p1p2 <= (others => '0');
|
| 198 |
|
|
EX_data_hilo <= (others => '0');
|
| 199 |
|
|
elsif stop_all2 = '0' then -- sinal stop_all do pipe 2
|
| 200 |
|
|
EX_data_hilo <= hilo_p1p2_s;
|
| 201 |
|
|
EX_adresse_p1p2 <= bus32(unsigned(ex_address_p1p2) + 4); --*** endereco alvo para o pipe 2 ***
|
| 202 |
|
|
end if;
|
| 203 |
|
|
|
| 204 |
|
|
end if;
|
| 205 |
|
|
end process;
|
| 206 |
|
|
|
| 207 |
|
|
end architecture;
|
