| 1 |
37 |
mcafruni |
------------------------------------------------------------------------------------
|
| 2 |
|
|
-- --
|
| 3 |
|
|
-- Copyright (c) 2004, Hangouet Samuel --
|
| 4 |
|
|
-- , Jan Sebastien --
|
| 5 |
|
|
-- , Mouton Louis-Marie --
|
| 6 |
|
|
-- , Schneider Olivier all rights reserved --
|
| 7 |
|
|
-- --
|
| 8 |
|
|
-- This file is part of miniMIPS. --
|
| 9 |
|
|
-- --
|
| 10 |
|
|
-- miniMIPS is free software; you can redistribute it and/or modify --
|
| 11 |
|
|
-- it under the terms of the GNU General Public License as published by --
|
| 12 |
|
|
-- the Free Software Foundation; either version 2 of the License, or --
|
| 13 |
|
|
-- (at your option) any later version. --
|
| 14 |
|
|
-- --
|
| 15 |
|
|
-- miniMIPS is distributed in the hope that it will be useful, --
|
| 16 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
|
| 17 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
|
| 18 |
|
|
-- GNU General Public License for more details. --
|
| 19 |
|
|
-- --
|
| 20 |
|
|
-- You should have received a copy of the GNU General Public License --
|
| 21 |
|
|
-- along with miniMIPS; if not, write to the Free Software --
|
| 22 |
|
|
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
|
| 23 |
|
|
-- --
|
| 24 |
|
|
------------------------------------------------------------------------------------
|
| 25 |
|
|
|
| 26 |
|
|
|
| 27 |
|
|
-- If you encountered any problem, please contact :
|
| 28 |
|
|
--
|
| 29 |
|
|
-- lmouton@enserg.fr
|
| 30 |
|
|
-- oschneid@enserg.fr
|
| 31 |
|
|
-- shangoue@enserg.fr
|
| 32 |
|
|
--
|
| 33 |
|
|
|
| 34 |
|
|
|
| 35 |
|
|
|
| 36 |
|
|
--------------------------------------------------------------------------
|
| 37 |
|
|
-- --
|
| 38 |
|
|
-- --
|
| 39 |
|
|
-- miniMIPS Processor : Address calculation stage --
|
| 40 |
|
|
-- --
|
| 41 |
|
|
-- --
|
| 42 |
|
|
-- --
|
| 43 |
|
|
-- Authors : Hangouet Samuel --
|
| 44 |
|
|
-- Jan Sébastien --
|
| 45 |
|
|
-- Mouton Louis-Marie --
|
| 46 |
|
|
-- Schneider Olivier --
|
| 47 |
|
|
-- --
|
| 48 |
|
|
-- june 2003 --
|
| 49 |
|
|
--------------------------------------------------------------------------
|
| 50 |
|
|
|
| 51 |
|
|
library IEEE;
|
| 52 |
|
|
use IEEE.std_logic_1164.all;
|
| 53 |
|
|
use IEEE.numeric_std.all;
|
| 54 |
|
|
|
| 55 |
|
|
library work;
|
| 56 |
|
|
use work.pack_mips.all;
|
| 57 |
|
|
|
| 58 |
|
|
entity pps_pf is
|
| 59 |
|
|
port (
|
| 60 |
|
|
clock : in bus1;
|
| 61 |
|
|
clock2 : in bus1;
|
| 62 |
|
|
reset : in bus1;
|
| 63 |
|
|
stop_all : in bus1; -- Unconditionnal locking of the pipeline stage
|
| 64 |
|
|
stop_all2 : in bus1;
|
| 65 |
|
|
|
| 66 |
|
|
-- Asynchronous inputs
|
| 67 |
|
|
bra_cmd : in bus1; -- Branch
|
| 68 |
|
|
bra_adr : in bus32; -- Address to load when an effective branch
|
| 69 |
|
|
exch_cmd : in bus1; -- Exception branch
|
| 70 |
|
|
exch_adr : in bus32; -- Exception vector
|
| 71 |
|
|
-- Asynchronous inputs 2
|
| 72 |
|
|
bra_cmd2 : in bus1; -- Branch
|
| 73 |
|
|
bra_adr2 : in bus32; -- Address to load when an effective branch
|
| 74 |
|
|
exch_cmd2 : in bus1; -- Exception branch
|
| 75 |
|
|
exch_adr2 : in bus32; -- Exception vector
|
| 76 |
|
|
|
| 77 |
|
|
stop_pf : in bus1; -- Lock the stage
|
| 78 |
|
|
stop_pf2 : in bus1; -- Lock the stage
|
| 79 |
|
|
-- Synchronous output to EI stage
|
| 80 |
|
|
PF_pc : out bus32; -- PC value
|
| 81 |
|
|
PF_pc_4 : out bus32 -- PC+4 value
|
| 82 |
|
|
);
|
| 83 |
|
|
end pps_pf;
|
| 84 |
|
|
|
| 85 |
|
|
architecture rtl of pps_pf is
|
| 86 |
|
|
|
| 87 |
|
|
signal suivant : bus32; -- Preparation of the future pc
|
| 88 |
|
|
signal suivant4 : bus32; -- Preparation of the future pc
|
| 89 |
|
|
signal pc_interne : bus32; -- Value of the pc output, needed for an internal reading
|
| 90 |
|
|
signal pc_interne4 : bus32; -- Value of the pc output, needed for an internal reading
|
| 91 |
|
|
signal lock : bus1; -- Specify the authorization of the pc evolution
|
| 92 |
|
|
signal lock2 : bus1; -- independente para o pipe 2, 06.02.18
|
| 93 |
|
|
|
| 94 |
|
|
begin
|
| 95 |
|
|
-- Connexion the pc to the internal pc
|
| 96 |
|
|
PF_pc <= pc_interne;
|
| 97 |
|
|
PF_pc_4 <= pc_interne4;
|
| 98 |
|
|
|
| 99 |
|
|
-- Elaboration of an potential future pc
|
| 100 |
|
|
suivant <= exch_adr when exch_cmd = '1' else
|
| 101 |
|
|
bus32(unsigned(exch_adr2) + 4) when exch_cmd2 = '1' else
|
| 102 |
|
|
bra_adr when bra_cmd = '1' else
|
| 103 |
|
|
bus32(unsigned(pc_interne) + 8);
|
| 104 |
|
|
|
| 105 |
|
|
suivant4 <= exch_adr2 when exch_cmd2 = '1' else
|
| 106 |
|
|
bus32(unsigned(exch_adr) + 4) when exch_cmd = '1' else
|
| 107 |
|
|
bra_adr2 when bra_cmd2 = '1' else
|
| 108 |
|
|
bus32(unsigned(pc_interne4) + 8);
|
| 109 |
|
|
|
| 110 |
|
|
|
| 111 |
|
|
lock <= '1' when stop_all = '1' else -- Lock this stage when all the pipeline is locked
|
| 112 |
|
|
'0' when exch_cmd = '1' else -- Exception
|
| 113 |
|
|
'0' when exch_cmd2 = '1' else -- Exception
|
| 114 |
|
|
'0' when bra_cmd = '1' else -- Branch
|
| 115 |
|
|
'0' when bra_cmd2 = '1' else -- Branch
|
| 116 |
|
|
'1' when stop_pf = '1' else -- Wait for the branch hazard
|
| 117 |
|
|
'0'; -- Normal evolution
|
| 118 |
|
|
|
| 119 |
|
|
lock2 <= '1' when stop_all2 = '1' else -- Lock this stage when all the pipeline is locked
|
| 120 |
|
|
'0' when exch_cmd2 = '1' else -- Exception
|
| 121 |
|
|
'0' when exch_cmd = '1' else -- Exception
|
| 122 |
|
|
'0' when bra_cmd2 = '1' else -- Branch
|
| 123 |
|
|
'0' when bra_cmd = '1' else -- Branch
|
| 124 |
|
|
'1' when stop_pf2 = '1' else -- Wait for the branch hazard
|
| 125 |
|
|
'0'; -- Normal evolution
|
| 126 |
|
|
|
| 127 |
|
|
-- Synchronous evolution of the pc
|
| 128 |
|
|
process(clock)
|
| 129 |
|
|
begin
|
| 130 |
|
|
if rising_edge(clock) then
|
| 131 |
|
|
if reset='1' then
|
| 132 |
|
|
-- PC reinitialisation with the boot address
|
| 133 |
|
|
pc_interne <= ADR_INIT;
|
| 134 |
|
|
elsif lock='0' then
|
| 135 |
|
|
-- PC not locked
|
| 136 |
|
|
pc_interne <= suivant;
|
| 137 |
|
|
end if;
|
| 138 |
|
|
end if;
|
| 139 |
|
|
end process;
|
| 140 |
|
|
|
| 141 |
|
|
process(clock2)
|
| 142 |
|
|
begin
|
| 143 |
|
|
if rising_edge(clock2) then
|
| 144 |
|
|
if reset='1' then
|
| 145 |
|
|
-- PC reinitialisation with the boot address
|
| 146 |
|
|
pc_interne4 <= ADR_INIT4;
|
| 147 |
|
|
elsif (lock2='0') then
|
| 148 |
|
|
-- PC not locked
|
| 149 |
|
|
pc_interne4 <= suivant4;
|
| 150 |
|
|
end if;
|
| 151 |
|
|
end if;
|
| 152 |
|
|
end process;
|
| 153 |
|
|
|
| 154 |
|
|
end rtl;
|
