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[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] [blackboxes/] [or1200_top.v] - Blame information for rev 113

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1 63 rfajardo
 
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`include "or1200_defines.v"
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module or1200_top(
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        // System
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        clk_i, rst_i, pic_ints_i, clmode_i,
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        // Instruction WISHBONE INTERFACE
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        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
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        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
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`ifdef OR1200_WB_CAB
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        iwb_cab_o,
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`endif
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`ifdef OR1200_WB_B3
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        iwb_cti_o, iwb_bte_o,
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`endif
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        // Data WISHBONE INTERFACE
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        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
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        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
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`ifdef OR1200_WB_CAB
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        dwb_cab_o,
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`endif
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`ifdef OR1200_WB_B3
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        dwb_cti_o, dwb_bte_o,
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`endif
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        // External Debug Interface
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        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
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        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
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`ifdef OR1200_BIST
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        // RAM BIST
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        mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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        // Power Management
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        pm_cpustall_i,
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        pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
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        pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter ppic_ints = `OR1200_PIC_INTS;
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//
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// I/O
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//
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//
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// System
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//
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input                   clk_i;
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input                   rst_i;
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input   [1:0]            clmode_i;       // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
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input   [ppic_ints-1:0]  pic_ints_i;
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//
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// Instruction WISHBONE interface
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//
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input                   iwb_clk_i;      // clock input
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input                   iwb_rst_i;      // reset input
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input                   iwb_ack_i;      // normal termination
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input                   iwb_err_i;      // termination w/ error
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input                   iwb_rty_i;      // termination w/ retry
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input   [dw-1:0] iwb_dat_i;      // input data bus
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output                  iwb_cyc_o;      // cycle valid output
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output  [aw-1:0] iwb_adr_o;      // address bus outputs
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output                  iwb_stb_o;      // strobe output
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output                  iwb_we_o;       // indicates write transfer
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output  [3:0]            iwb_sel_o;      // byte select outputs
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output  [dw-1:0] iwb_dat_o;      // output data bus
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`ifdef OR1200_WB_CAB
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output                  iwb_cab_o;      // indicates consecutive address burst
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`endif
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`ifdef OR1200_WB_B3
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output  [2:0]            iwb_cti_o;      // cycle type identifier
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output  [1:0]            iwb_bte_o;      // burst type extension
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`endif
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//
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// Data WISHBONE interface
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//
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input                   dwb_clk_i;      // clock input
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input                   dwb_rst_i;      // reset input
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input                   dwb_ack_i;      // normal termination
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input                   dwb_err_i;      // termination w/ error
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input                   dwb_rty_i;      // termination w/ retry
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input   [dw-1:0] dwb_dat_i;      // input data bus
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output                  dwb_cyc_o;      // cycle valid output
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output  [aw-1:0] dwb_adr_o;      // address bus outputs
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output                  dwb_stb_o;      // strobe output
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output                  dwb_we_o;       // indicates write transfer
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output  [3:0]            dwb_sel_o;      // byte select outputs
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output  [dw-1:0] dwb_dat_o;      // output data bus
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`ifdef OR1200_WB_CAB
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output                  dwb_cab_o;      // indicates consecutive address burst
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`endif
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`ifdef OR1200_WB_B3
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output  [2:0]            dwb_cti_o;      // cycle type identifier
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output  [1:0]            dwb_bte_o;      // burst type extension
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`endif
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//
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// External Debug Interface
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//
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input                   dbg_stall_i;    // External Stall Input
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input                   dbg_ewt_i;      // External Watchpoint Trigger Input
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output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
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output  [1:0]            dbg_is_o;       // External Insn Fetch Status
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output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
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output                  dbg_bp_o;       // Breakpoint Output
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input                   dbg_stb_i;      // External Address/Data Strobe
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input                   dbg_we_i;       // External Write Enable
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input   [aw-1:0] dbg_adr_i;      // External Address Input
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input   [dw-1:0] dbg_dat_i;      // External Data Input
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output  [dw-1:0] dbg_dat_o;      // External Data Output
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output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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`endif
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//
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// Power Management
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//
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input                   pm_cpustall_i;
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output  [3:0]            pm_clksd_o;
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output                  pm_dc_gate_o;
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output                  pm_ic_gate_o;
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output                  pm_dmmu_gate_o;
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output                  pm_immu_gate_o;
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output                  pm_tt_gate_o;
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output                  pm_cpu_gate_o;
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output                  pm_wakeup_o;
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output                  pm_lvolt_o;
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endmodule

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