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Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] [minsoc_bench.prj] - Blame information for rev 128

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Line No. Rev Author Line
1 88 rfajardo
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog)
2
PROJECT_SRC=(minsoc_bench_defines.v
3 128 rfajardo
minsoc_bench_clock.v
4 88 rfajardo
minsoc_bench.v
5
minsoc_memory_model.v
6
dbg_comm_vpi.v
7
fpga_memory_primitives.v
8
timescale.v)
9
 

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