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[/] [minsoc/] [branches/] [rc-1.0/] [sim/] [modelsim/] [compile_design.sh] - Blame information for rev 132

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Line No. Rev Author Line
1 70 rfajardo
#!/bin/bash
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3 104 rfajardo
vlog -incr -work minsoc -f ../../prj/sim/minsoc_verilog.src
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#vcom -work minsoc -f ../../prj/sim/minsoc_vhdl.src

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