OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [sw/] [drivers/] [uart.c] - Blame information for rev 147

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 80 rfajardo
#include <board.h>
2
#include <support.h>
3 36 rfajardo
#include "uart.h"
4
 
5 53 ConX.
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
6
 
7
#define WAIT_FOR_XMITR \
8
        do { \
9
                lsr = REG8(UART_BASE + UART_LSR); \
10
        } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
11
 
12
#define WAIT_FOR_THRE \
13
        do { \
14
                lsr = REG8(UART_BASE + UART_LSR); \
15
        } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
16
 
17
#define CHECK_FOR_CHAR (REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
18
 
19
#define WAIT_FOR_CHAR \
20
        do { \
21
                lsr = REG8(UART_BASE + UART_LSR); \
22
        } while ((lsr & UART_LSR_DR) != UART_LSR_DR)
23
 
24
#define UART_TX_BUFF_LEN 32
25
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
26
 
27
char tx_buff[UART_TX_BUFF_LEN];
28
volatile int tx_level, rx_level;
29
 
30
void uart_init(void)
31
{
32
        int divisor;
33
 
34
        /* Reset receiver and transmiter */
35
        /* Set RX interrupt for each byte */
36
        REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
37
 
38
        /* Enable RX interrupt */
39
        REG8(UART_BASE + UART_IER) = UART_IER_RDI | UART_IER_THRI;
40
 
41
        /* Set 8 bit char, 1 stop bit, no parity */
42
        REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
43
 
44
        /* Set baud rate */
45
        divisor = IN_CLK/(16 * UART_BAUD_RATE);
46
        REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
47
        REG8(UART_BASE + UART_DLM) = (divisor >> 8) & 0x000000ff;
48
        REG8(UART_BASE + UART_DLL) = divisor & 0x000000ff;
49
        REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
50
 
51
        return;
52
}
53
 
54
void uart_putc(char c)
55
{
56
        unsigned char lsr;
57
 
58
        WAIT_FOR_THRE;
59
        REG8(UART_BASE + UART_TX) = c;
60
        WAIT_FOR_XMITR;
61
}
62
 
63
 
64
 
65
char uart_getc()
66
{
67
        char c;
68
        c = REG8(UART_BASE + UART_RX);
69
        return c;
70
}
71
 
72
 
73 36 rfajardo
void uart_interrupt()
74
{
75 53 ConX.
        char lala;
76
        unsigned char interrupt_id;
77
        interrupt_id = REG8(UART_BASE + UART_IIR);
78
        if ( interrupt_id & UART_IIR_RDI )
79
        {
80
                lala = uart_getc();
81
                uart_putc(lala+1);
82
        }
83 36 rfajardo
 
84
}
85
 
86
void uart_print_str(char *p)
87
{
88 53 ConX.
        while(*p != 0) {
89
                uart_putc(*p);
90
                p++;
91
        }
92 36 rfajardo
}
93
 
94
void uart_print_long(unsigned long ul)
95
{
96 53 ConX.
        int i;
97
        char c;
98 36 rfajardo
 
99
 
100 53 ConX.
        uart_print_str("0x");
101
        for(i=0; i<8; i++) {
102 36 rfajardo
 
103 53 ConX.
                c = (char) (ul>>((7-i)*4)) & 0xf;
104
                if(c >= 0x0 && c<=0x9)
105
                        c += '0';
106
                else
107
                        c += 'a' - 10;
108
                uart_putc(c);
109
        }
110
 
111 36 rfajardo
}
112
 
113
void uart_print_short(unsigned long ul)
114
{
115 53 ConX.
        int i;
116
        char c;
117
        char flag=0;
118 36 rfajardo
 
119
 
120 53 ConX.
        uart_print_str("0x");
121
        for(i=0; i<8; i++) {
122 36 rfajardo
 
123 53 ConX.
                c = (char) (ul>>((7-i)*4)) & 0xf;
124
                if(c >= 0x0 && c<=0x9)
125
                        c += '0';
126
                else
127
                        c += 'a' - 10;
128
                if ((c != '0') || (i==7))
129
                        flag=1;
130
                if(flag)
131
                        uart_putc(c);
132
        }
133
 
134 36 rfajardo
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.