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[/] [minsoc/] [branches/] [rc-1.0/] [utils/] [setup/] [or1200v1_hwbkpt.patch] - Blame information for rev 121

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Line No. Rev Author Line
1 121 rfajardo
--- ../../../Bennu/Hardware/or1200v1/rtl/verilog/or1200_defines.v       2010-08-25 23:25:38.000000000 -0500
2
+++ ./or1200_defines.v  2010-08-26 21:31:42.000000000 -0500
3
@@ -971,7 +971,7 @@
4
 // however already enough for use
5
 // with or32 gdb)
6
 //
7
-//`define OR1200_DU_HWBKPTS
8
+`define OR1200_DU_HWBKPTS
9
 
10
 // Number of DVR/DCR pairs if HW breakpoints enabled
11
 `define OR1200_DU_DVRDCR_PAIRS 8
12
@@ -1038,17 +1038,15 @@
13
 `define OR1200_DU_DMR1_CW7     15:14
14
 `define OR1200_DU_DMR1_CW8     17:16
15
 `define OR1200_DU_DMR1_CW9     19:18
16
-`define OR1200_DU_DMR1_CW10    21:20
17
+`define OR1200_DU_DMR1_RES     21:20
18
 `define OR1200_DU_DMR1_ST      22
19
 `define OR1200_DU_DMR1_BT      23
20
-`define OR1200_DU_DMR1_DXFW    24
21
-`define OR1200_DU_DMR1_ETE     25
22
 
23
 // DMR2 bits
24
 `define OR1200_DU_DMR2_WCE0    0
25
 `define OR1200_DU_DMR2_WCE1    1
26
-`define OR1200_DU_DMR2_AWTC    12:2
27
-`define OR1200_DU_DMR2_WGB     23:13
28
+`define OR1200_DU_DMR2_AWTC    11:2
29
+`define OR1200_DU_DMR2_WGB     21:12
30
 
31
 // DWCR bits
32
 `define OR1200_DU_DWCR_COUNT   15:0
33
--- /cygdrive/c/Projects/Bennu/Hardware/or1200v1/rtl/verilog/or1200_top.v       2010-08-25 23:25:40.000000000 -0500
34
+++ ./or1200_top.v      2010-06-12 16:59:02.000000000 -0500
35
@@ -43,6 +43,13 @@
36
 //
37
 // CVS Revision History
38
 //
39
+// $Log: or1200v1_hwbkpt.patch,v $
40
+// Revision 1.1  2010-08-27 02:43:07  Nathan
41
+// Moved patches for third-party software to a separate, dedicated directory structure.
42
+//
43
+// Revision 1.13  2004/06/08 18:17:36  lampret
44
+// Non-functional changes. Coding style fixes.
45
+//
46
 // $Log: not supported by cvs2svn $
47
 // Revision 1.12  2004/04/05 08:29:57  lampret
48
 // Merged branch_qmem into main tree.
49
@@ -933,6 +936,7 @@ or1200_du or1200_du(
50
        .dcpu_cycstb_i(dcpu_cycstb_cpu),
51
        .dcpu_we_i(dcpu_we_cpu),
52
        .dcpu_adr_i(dcpu_adr_cpu),
53
+       .dcpu_be_i(dcpu_sel_cpu),
54
        .dcpu_dat_lsu(dcpu_dat_cpu),
55
        .dcpu_dat_dc(dcpu_dat_qmem),
56
        .icpu_cycstb_i(icpu_cycstb_cpu),
57
--- /cygdrive/c/Projects/Bennu/Hardware/or1200v1/rtl/verilog/or1200_du.v        2010-08-25 23:25:38.000000000 -0500
58
+++ ./or1200_du.v       2010-08-26 21:28:32.000000000 -0500
59
@@ -124,8 +124,8 @@
60
 module or1200_du(
61
        // RISC Internal Interface
62
        clk, rst,
63
-       dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
64
-       dcpu_dat_dc, icpu_cycstb_i,
65
+       dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_be_i,
66
+       dcpu_dat_lsu, dcpu_dat_dc, icpu_cycstb_i,
67
        ex_freeze, branch_op, ex_insn, id_pc,
68
        spr_dat_npc, rf_dataw,
69
        du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
70
@@ -152,6 +152,7 @@ input                               rst;            // Reset
71
 input                          dcpu_cycstb_i;  // LSU status
72
 input                          dcpu_we_i;      // LSU status
73
 input  [31:0]                  dcpu_adr_i;     // LSU addr
74
+input   [3:0]       dcpu_be_i;
75
 input  [31:0]                  dcpu_dat_lsu;   // LSU store data
76
 input  [31:0]                  dcpu_dat_dc;    // LSU load data
77
 input  [`OR1200_FETCHOP_WIDTH-1:0]     icpu_cycstb_i;  // IFETCH unit status
78
@@ -192,6 +193,7 @@ input       [dw-1:0]        dbg_dat_i;      // External Da
79
 output [dw-1:0]        dbg_dat_o;      // External Data Output
80
 output                 dbg_ack_o;      // External Data Acknowledge (not WB compatible)
81
 
82
+reg    [9:0]           wp;
83
 
84
 //
85
 // Some connections go directly from the CPU through DU to Debug I/F
86
@@ -216,7 +218,7 @@ assign dbg_is_o = 2'b00;
87
 assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
88
 assign dbg_is_o = {1'b0, icpu_cycstb_i};
89
 `endif
90
-assign dbg_wp_o = 11'b000_0000_0000;
91
+assign dbg_wp_o = {1'b0, wp};  //11'b000_0000_0000;
92
 assign dbg_dat_o = du_dat_i;
93
 
94
 //
95
@@ -253,9 +255,9 @@ wire        [24:0]                  dmr1;           // DMR1 not impleme
96
 // Debug Mode Register 2
97
 //
98
 `ifdef OR1200_DU_DMR2
99
-reg    [23:0]                  dmr2;           // DMR2 implemented
100
+reg    [21:0]                  dmr2;           // DMR2 implemented
101
 `else
102
-wire   [23:0]                  dmr2;           // DMR2 not implemented
103
+wire   [21:0]                  dmr2;           // DMR2 not implemented
104
 `endif
105
 
106
 //
107
@@ -473,6 +475,14 @@ reg        [31:0]                  match_cond4_ct;
108
 reg    [31:0]                  match_cond5_ct;
109
 reg    [31:0]                  match_cond6_ct;
110
 reg    [31:0]                  match_cond7_ct;
111
+reg    [31:0]                  match_cond0_tmp;
112
+reg    [31:0]                  match_cond1_tmp;
113
+reg    [31:0]                  match_cond2_tmp;
114
+reg    [31:0]                  match_cond3_tmp;
115
+reg    [31:0]                  match_cond4_tmp;
116
+reg    [31:0]                  match_cond5_tmp;
117
+reg    [31:0]                  match_cond6_tmp;
118
+reg    [31:0]                  match_cond7_tmp;
119
 reg                            match_cond0_stb;
120
 reg                            match_cond1_stb;
121
 reg                            match_cond2_stb;
122
@@ -491,9 +501,16 @@ reg                                match6;
123
 reg                            match7;
124
 reg                            wpcntr0_match;
125
 reg                            wpcntr1_match;
126
-reg                            incr_wpcntr0;
127
-reg                            incr_wpcntr1;
128
-reg    [10:0]                  wp;
129
+reg             wpcntr0_armed;
130
+reg             wpcntr0_oneshot;
131
+reg             wpcntr1_armed;
132
+reg             wpcntr1_oneshot;
133
+wire                   incr_wpcntr0;
134
+reg             incr_wpcntr0_latched;
135
+wire            incr_wpcntr1;
136
+reg             incr_wpcntr1_latched;
137
+reg             du_hwbkpt_latched;
138
+reg [9:0]       wp_latched;
139
 `endif
140
 wire                           du_hwbkpt;
141
 `ifdef OR1200_DU_READREGS
142
@@ -670,11 +687,11 @@ assign dmr1 = 25'h000_0000;
143
 `ifdef OR1200_DU_DMR2
144
 always @(posedge clk or posedge rst)
145
        if (rst)
146
-               dmr2 <= 24'h00_0000;
147
+               dmr2 <= 22'h00_0000;
148
        else if (dmr2_sel && spr_write)
149
-               dmr2 <= #1 spr_dat_i[23:0];
150
+               dmr2 <= #1 spr_dat_i[21:0];
151
 `else
152
-assign dmr2 = 24'h00_0000;
153
+assign dmr2 = 22'h00_0000;
154
 `endif
155
 
156
 //
157
@@ -815,9 +832,9 @@ assign dvr7 = 32'h0000_0000;
158
 `ifdef OR1200_DU_DCR0
159
 always @(posedge clk or posedge rst)
160
        if (rst)
161
-               dcr0 <= 8'h00;
162
+               dcr0 <= 8'h01;
163
        else if (dcr0_sel && spr_write)
164
-               dcr0 <= #1 spr_dat_i[7:0];
165
+               dcr0 <= #1 {spr_dat_i[7:1], 1'b1};
166
 `else
167
 assign dcr0 = 8'h00;
168
 `endif
169
@@ -828,9 +845,9 @@ assign dcr0 = 8'h00;
170
 `ifdef OR1200_DU_DCR1
171
 always @(posedge clk or posedge rst)
172
        if (rst)
173
-               dcr1 <= 8'h00;
174
+               dcr1 <= 8'h01;
175
        else if (dcr1_sel && spr_write)
176
-               dcr1 <= #1 spr_dat_i[7:0];
177
+               dcr1 <= #1 {spr_dat_i[7:1], 1'b1};
178
 `else
179
 assign dcr1 = 8'h00;
180
 `endif
181
@@ -841,9 +858,9 @@ assign dcr1 = 8'h00;
182
 `ifdef OR1200_DU_DCR2
183
 always @(posedge clk or posedge rst)
184
        if (rst)
185
-               dcr2 <= 8'h00;
186
+               dcr2 <= 8'h01;
187
        else if (dcr2_sel && spr_write)
188
-               dcr2 <= #1 spr_dat_i[7:0];
189
+               dcr2 <= #1 {spr_dat_i[7:1], 1'b1};
190
 `else
191
 assign dcr2 = 8'h00;
192
 `endif
193
@@ -854,9 +871,9 @@ assign dcr2 = 8'h00;
194
 `ifdef OR1200_DU_DCR3
195
 always @(posedge clk or posedge rst)
196
        if (rst)
197
-               dcr3 <= 8'h00;
198
+               dcr3 <= 8'h01;
199
        else if (dcr3_sel && spr_write)
200
-               dcr3 <= #1 spr_dat_i[7:0];
201
+               dcr3 <= #1 {spr_dat_i[7:1], 1'b1};
202
 `else
203
 assign dcr3 = 8'h00;
204
 `endif
205
@@ -867,9 +884,9 @@ assign dcr3 = 8'h00;
206
 `ifdef OR1200_DU_DCR4
207
 always @(posedge clk or posedge rst)
208
        if (rst)
209
-               dcr4 <= 8'h00;
210
+               dcr4 <= 8'h01;
211
        else if (dcr4_sel && spr_write)
212
-               dcr4 <= #1 spr_dat_i[7:0];
213
+               dcr4 <= #1 {spr_dat_i[7:1], 1'b1};
214
 `else
215
 assign dcr4 = 8'h00;
216
 `endif
217
@@ -880,9 +897,9 @@ assign dcr4 = 8'h00;
218
 `ifdef OR1200_DU_DCR5
219
 always @(posedge clk or posedge rst)
220
        if (rst)
221
-               dcr5 <= 8'h00;
222
+               dcr5 <= 8'h01;
223
        else if (dcr5_sel && spr_write)
224
-               dcr5 <= #1 spr_dat_i[7:0];
225
+               dcr5 <= #1 {spr_dat_i[7:1], 1'b1};
226
 `else
227
 assign dcr5 = 8'h00;
228
 `endif
229
@@ -893,9 +910,9 @@ assign dcr5 = 8'h00;
230
 `ifdef OR1200_DU_DCR6
231
 always @(posedge clk or posedge rst)
232
        if (rst)
233
-               dcr6 <= 8'h00;
234
+               dcr6 <= 8'h01;
235
        else if (dcr6_sel && spr_write)
236
-               dcr6 <= #1 spr_dat_i[7:0];
237
+               dcr6 <= #1 {spr_dat_i[7:1], 1'b1};
238
 `else
239
 assign dcr6 = 8'h00;
240
 `endif
241
@@ -906,9 +923,9 @@ assign dcr6 = 8'h00;
242
 `ifdef OR1200_DU_DCR7
243
 always @(posedge clk or posedge rst)
244
        if (rst)
245
-               dcr7 <= 8'h00;
246
+               dcr7 <= 8'h01;
247
        else if (dcr7_sel && spr_write)
248
-               dcr7 <= #1 spr_dat_i[7:0];
249
+               dcr7 <= #1 {spr_dat_i[7:1], 1'b1};
250
 `else
251
 assign dcr7 = 8'h00;
252
 `endif
253
@@ -952,7 +969,7 @@ always @(spr_addr or dsr or drr or dmr1
254
        or dvr5 or dvr6 or dvr7
255
        or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
256
        or dcr5 or dcr6 or dcr7
257
-       or dwcr0 or dwcr1
258
+       or dwcr0 or dwcr1 or wp_latched
259
 `ifdef OR1200_DU_TB_IMPLEMENTED
260
        or tb_wadr or tbia_dat_o or tbim_dat_o
261
        or tbar_dat_o or tbts_dat_o
262
@@ -1029,7 +1046,7 @@ always @(spr_addr or dsr or drr or dmr1
263
 `endif
264
 `ifdef OR1200_DU_DMR2
265
                `OR1200_DU_DMR2:
266
-                       spr_dat_o = {8'h00, dmr2};
267
+                       spr_dat_o = {wp_latched, dmr2};
268
 `endif
269
 `ifdef OR1200_DU_DWCR0
270
                `OR1200_DU_DWCR0:
271
@@ -1077,23 +1094,50 @@ assign du_dsr = dsr;
272
 always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
273
        or dcpu_dat_lsu or dcpu_we_i)
274
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
275
-               3'b001: match_cond0_ct = id_pc;         // insn fetch EA
276
-               3'b010: match_cond0_ct = dcpu_adr_i;    // load EA
277
-               3'b011: match_cond0_ct = dcpu_adr_i;    // store EA
278
-               3'b100: match_cond0_ct = dcpu_dat_dc;   // load data
279
-               3'b101: match_cond0_ct = dcpu_dat_lsu;  // store data
280
-               3'b110: match_cond0_ct = dcpu_adr_i;    // load/store EA
281
-               default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
282
-       endcase
283
+               3'b001: match_cond0_tmp = id_pc;                // insn fetch EA
284
+               3'b010: match_cond0_tmp = dcpu_adr_i;   // load EA
285
+               3'b011: match_cond0_tmp = dcpu_adr_i;   // store EA
286
+               3'b100: match_cond0_tmp = dcpu_dat_dc;  // load data
287
+               3'b101: match_cond0_tmp = dcpu_dat_lsu; // store data
288
+               3'b110: match_cond0_tmp = dcpu_adr_i;   // load/store EA
289
+               default:match_cond0_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
290
+       endcase
291
+
292
+// Transparently handle 8/16/32 bit bus accesses (Match Condition 0)
293
+// For addresses, leave unchanged
294
+// for 32-bit data, leave unchanged
295
+// for 8- or 16-bit data, move the active byte lane(s) to the LSB position
296
+// This will allow the value to be compared to the LSB(s) of the DVR
297
+always @(match_cond0_tmp or dcr0 or dcpu_be_i)
298
+  case (dcr0[`OR1200_DU_DCR_CT])               // synopsys parallel_case
299
+    3'b100,
300
+    3'b101,
301
+    3'b111:  begin // We're comparing to data
302
+      case (dcpu_be_i)
303
+        4'b1000: match_cond0_ct = { {24{dcr0[`OR1200_DU_DCR_SC] & match_cond0_tmp[31]}}, match_cond0_tmp[31:24]};
304
+        4'b0100: match_cond0_ct = { {24{dcr0[`OR1200_DU_DCR_SC] & match_cond0_tmp[23]}}, match_cond0_tmp[23:16]};
305
+        4'b0010: match_cond0_ct = { {24{dcr0[`OR1200_DU_DCR_SC] & match_cond0_tmp[15]}}, match_cond0_tmp[15:8]};
306
+        4'b0001: match_cond0_ct = { {24{dcr0[`OR1200_DU_DCR_SC] & match_cond0_tmp[7] }}, match_cond0_tmp[7:0]};
307
+        4'b1100: match_cond0_ct = { {16{dcr0[`OR1200_DU_DCR_SC] & match_cond0_tmp[31]}}, match_cond0_tmp[31:16]};
308
+        4'b0011: match_cond0_ct = { {16{dcr0[`OR1200_DU_DCR_SC] & match_cond0_tmp[15]}}, match_cond0_tmp[15:0]};
309
+        default: match_cond0_ct = match_cond0_tmp;
310
+      endcase
311
+    end
312
+    default: match_cond0_ct = match_cond0_tmp;  // We're comparing an address
313
+  endcase
314
 
315
 //
316
 // When To Compare (Match Condition 0)
317
 //
318
-always @(dcr0 or dcpu_cycstb_i)
319
-       case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
320
+always @(dcr0 or dcpu_cycstb_i or dcpu_we_i)
321
+       case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
322
                3'b000: match_cond0_stb = 1'b0;         //comparison disabled
323
                3'b001: match_cond0_stb = 1'b1;         // insn fetch EA
324
-               default:match_cond0_stb = dcpu_cycstb_i; // any load/store
325
+               3'b010: match_cond0_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load addr
326
+               3'b011: match_cond0_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store addr
327
+               3'b100: match_cond0_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load val
328
+               3'b101: match_cond0_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store val
329
+               default: match_cond0_stb = dcpu_cycstb_i; // any load/store
330
        endcase
331
 
332
 //
333
@@ -1105,33 +1149,32 @@ always @(match_cond0_stb or dcr0 or dvr0
334
                4'b1_000,
335
                4'b1_111: match0 = 1'b0;
336
                4'b1_001: match0 =
337
-                       ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) ==
338
-                       (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
339
+                       (match_cond0_ct == dvr0);
340
                4'b1_010: match0 =
341
-                       ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <
342
-                       (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
343
+                       ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <
344
+                        {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]} );
345
                4'b1_011: match0 =
346
-                       ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <=
347
-                       (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
348
+                       ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <=
349
+                        {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]} );
350
                4'b1_100: match0 =
351
-                       ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >
352
-                       (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
353
+                       ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >
354
+                        {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]} );
355
                4'b1_101: match0 =
356
-                       ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >=
357
-                       (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
358
+                       ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >=
359
+                        {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]} );
360
                4'b1_110: match0 =
361
-                       ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) !=
362
-                       (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
363
+                       (match_cond0_ct != dvr0);
364
        endcase
365
 
366
+
367
 //
368
 // Watchpoint 0
369
 //
370
-always @(dmr1 or match0)
371
+always @(dmr1 or match0 or dbg_ewt_i)
372
        case (dmr1[`OR1200_DU_DMR1_CW0])
373
                2'b00: wp[0] = match0;
374
-               2'b01: wp[0] = match0;
375
-               2'b10: wp[0] = match0;
376
+               2'b01: wp[0] = match0 &  dbg_ewt_i;
377
+               2'b10: wp[0] = match0 |  dbg_ewt_i;
378
                2'b11: wp[0] = 1'b0;
379
        endcase
380
 
381
@@ -1141,23 +1184,50 @@ always @(dmr1 or match0)
382
 always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
383
        or dcpu_dat_lsu or dcpu_we_i)
384
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
385
-               3'b001: match_cond1_ct = id_pc;         // insn fetch EA
386
-               3'b010: match_cond1_ct = dcpu_adr_i;    // load EA
387
-               3'b011: match_cond1_ct = dcpu_adr_i;    // store EA
388
-               3'b100: match_cond1_ct = dcpu_dat_dc;   // load data
389
-               3'b101: match_cond1_ct = dcpu_dat_lsu;  // store data
390
-               3'b110: match_cond1_ct = dcpu_adr_i;    // load/store EA
391
-               default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
392
-       endcase
393
+               3'b001: match_cond1_tmp = id_pc;                // insn fetch EA
394
+               3'b010: match_cond1_tmp = dcpu_adr_i;   // load EA
395
+               3'b011: match_cond1_tmp = dcpu_adr_i;   // store EA
396
+               3'b100: match_cond1_tmp = dcpu_dat_dc;  // load data
397
+               3'b101: match_cond1_tmp = dcpu_dat_lsu; // store data
398
+               3'b110: match_cond1_tmp = dcpu_adr_i;   // load/store EA
399
+               default:match_cond1_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
400
+       endcase
401
+
402
+// Transparently handle 8/16/32 bit bus accesses (Match Condition 1)
403
+// For addresses, leave unchanged
404
+// for 32-bit data, leave unchanged
405
+// for 8- or 16-bit data, move the active byte lane(s) to the LSB position
406
+// This will allow the value to be compared to the LSB(s) of the DVR
407
+always @(match_cond1_tmp or dcr1 or dcpu_be_i)
408
+  case (dcr1[`OR1200_DU_DCR_CT])               // synopsys parallel_case
409
+    3'b100,
410
+    3'b101,
411
+    3'b111:  begin // We're comparing to data
412
+      case (dcpu_be_i)
413
+        4'b1000: match_cond1_ct = { {24{dcr1[`OR1200_DU_DCR_SC] & match_cond1_tmp[31]}}, match_cond1_tmp[31:24]};
414
+        4'b0100: match_cond1_ct = { {24{dcr1[`OR1200_DU_DCR_SC] & match_cond1_tmp[23]}}, match_cond1_tmp[23:16]};
415
+        4'b0010: match_cond1_ct = { {24{dcr1[`OR1200_DU_DCR_SC] & match_cond1_tmp[15]}}, match_cond1_tmp[15:8]};
416
+        4'b0001: match_cond1_ct = { {24{dcr1[`OR1200_DU_DCR_SC] & match_cond1_tmp[7] }}, match_cond1_tmp[7:0]};
417
+        4'b1100: match_cond1_ct = { {16{dcr1[`OR1200_DU_DCR_SC] & match_cond1_tmp[31]}}, match_cond1_tmp[31:16]};
418
+        4'b0011: match_cond1_ct = { {16{dcr1[`OR1200_DU_DCR_SC] & match_cond1_tmp[15]}}, match_cond1_tmp[15:0]};
419
+        default: match_cond1_ct = match_cond1_tmp;
420
+      endcase
421
+    end
422
+    default: match_cond1_ct = match_cond1_tmp;  // We're comparing an address
423
+  endcase
424
 
425
 //
426
 // When To Compare (Match Condition 1)
427
 //
428
-always @(dcr1 or dcpu_cycstb_i)
429
-       case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
430
+always @(dcr1 or dcpu_cycstb_i or dcpu_we_i)
431
+       case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
432
                3'b000: match_cond1_stb = 1'b0;         //comparison disabled
433
                3'b001: match_cond1_stb = 1'b1;         // insn fetch EA
434
-               default:match_cond1_stb = dcpu_cycstb_i; // any load/store
435
+               3'b010: match_cond1_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load addr
436
+               3'b011: match_cond1_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store addr
437
+               3'b100: match_cond1_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load val
438
+               3'b101: match_cond1_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store val
439
+               default: match_cond1_stb = dcpu_cycstb_i; // any load/store
440
        endcase
441
 
442
 //
443
@@ -1169,23 +1239,21 @@ always @(match_cond1_stb or dcr1 or dvr1
444
                4'b1_000,
445
                4'b1_111: match1 = 1'b0;
446
                4'b1_001: match1 =
447
-                       ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) ==
448
-                       (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
449
+                       (match_cond1_ct == dvr1);
450
                4'b1_010: match1 =
451
-                       ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <
452
-                       (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
453
+                       ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <
454
+                        {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]} );
455
                4'b1_011: match1 =
456
-                       ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <=
457
-                       (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
458
+                       ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <=
459
+                        {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]} );
460
                4'b1_100: match1 =
461
-                       ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >
462
-                       (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
463
+                       ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >
464
+                        {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]} );
465
                4'b1_101: match1 =
466
-                       ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >=
467
-                       (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
468
+                       ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >=
469
+                        {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]} );
470
                4'b1_110: match1 =
471
-                       ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) !=
472
-                       (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
473
+                       (match_cond1_ct != dvr1);
474
        endcase
475
 
476
 //
477
@@ -1199,29 +1267,57 @@ always @(dmr1 or match1 or wp)
478
                2'b11: wp[1] = 1'b0;
479
        endcase
480
 
481
+
482
 //
483
 // Compare To What (Match Condition 2)
484
 //
485
 always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
486
        or dcpu_dat_lsu or dcpu_we_i)
487
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
488
-               3'b001: match_cond2_ct = id_pc;         // insn fetch EA
489
-               3'b010: match_cond2_ct = dcpu_adr_i;    // load EA
490
-               3'b011: match_cond2_ct = dcpu_adr_i;    // store EA
491
-               3'b100: match_cond2_ct = dcpu_dat_dc;   // load data
492
-               3'b101: match_cond2_ct = dcpu_dat_lsu;  // store data
493
-               3'b110: match_cond2_ct = dcpu_adr_i;    // load/store EA
494
-               default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
495
-       endcase
496
+               3'b001: match_cond2_tmp = id_pc;                // insn fetch EA
497
+               3'b010: match_cond2_tmp = dcpu_adr_i;   // load EA
498
+               3'b011: match_cond2_tmp = dcpu_adr_i;   // store EA
499
+               3'b100: match_cond2_tmp = dcpu_dat_dc;  // load data
500
+               3'b101: match_cond2_tmp = dcpu_dat_lsu; // store data
501
+               3'b110: match_cond2_tmp = dcpu_adr_i;   // load/store EA
502
+               default:match_cond2_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
503
+       endcase
504
+
505
+// Transparently handle 8/16/32 bit bus accesses (Match Condition 2)
506
+// For addresses, leave unchanged
507
+// for 32-bit data, leave unchanged
508
+// for 8- or 16-bit data, move the active byte lane(s) to the LSB position
509
+// This will allow the value to be compared to the LSB(s) of the DVR
510
+always @(match_cond2_tmp or dcr2 or dcpu_be_i)
511
+  case (dcr2[`OR1200_DU_DCR_CT])               // synopsys parallel_case
512
+    3'b100,
513
+    3'b101,
514
+    3'b111:  begin // We're comparing to data
515
+      case (dcpu_be_i)
516
+        4'b1000: match_cond2_ct = { {24{dcr2[`OR1200_DU_DCR_SC] & match_cond2_tmp[31]}}, match_cond2_tmp[31:24]};
517
+        4'b0100: match_cond2_ct = { {24{dcr2[`OR1200_DU_DCR_SC] & match_cond2_tmp[23]}}, match_cond2_tmp[23:16]};
518
+        4'b0010: match_cond2_ct = { {24{dcr2[`OR1200_DU_DCR_SC] & match_cond2_tmp[15]}}, match_cond2_tmp[15:8]};
519
+        4'b0001: match_cond2_ct = { {24{dcr2[`OR1200_DU_DCR_SC] & match_cond2_tmp[7] }}, match_cond2_tmp[7:0]};
520
+        4'b1100: match_cond2_ct = { {16{dcr2[`OR1200_DU_DCR_SC] & match_cond2_tmp[31]}}, match_cond2_tmp[31:16]};
521
+        4'b0011: match_cond2_ct = { {16{dcr2[`OR1200_DU_DCR_SC] & match_cond2_tmp[15]}}, match_cond2_tmp[15:0]};
522
+        default: match_cond2_ct = match_cond2_tmp;
523
+      endcase
524
+    end
525
+    default: match_cond2_ct = match_cond2_tmp;  // We're comparing an address
526
+  endcase
527
 
528
 //
529
 // When To Compare (Match Condition 2)
530
 //
531
-always @(dcr2 or dcpu_cycstb_i)
532
-       case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
533
+always @(dcr2 or dcpu_cycstb_i or dcpu_we_i)
534
+       case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
535
                3'b000: match_cond2_stb = 1'b0;         //comparison disabled
536
                3'b001: match_cond2_stb = 1'b1;         // insn fetch EA
537
-               default:match_cond2_stb = dcpu_cycstb_i; // any load/store
538
+               3'b010: match_cond2_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load addr
539
+               3'b011: match_cond2_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store addr
540
+               3'b100: match_cond2_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load val
541
+               3'b101: match_cond2_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store val
542
+               default: match_cond2_stb = dcpu_cycstb_i; // any load/store
543
        endcase
544
 
545
 //
546
@@ -1233,23 +1329,21 @@ always @(match_cond2_stb or dcr2 or dvr2
547
                4'b1_000,
548
                4'b1_111: match2 = 1'b0;
549
                4'b1_001: match2 =
550
-                       ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) ==
551
-                       (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
552
+                       (match_cond2_ct == dvr2);
553
                4'b1_010: match2 =
554
-                       ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <
555
-                       (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
556
+                       ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <
557
+                        {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]} );
558
                4'b1_011: match2 =
559
-                       ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <=
560
-                       (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
561
+                       ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <=
562
+                        {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]} );
563
                4'b1_100: match2 =
564
-                       ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >
565
-                       (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
566
+                       ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >
567
+                        {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]} );
568
                4'b1_101: match2 =
569
-                       ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >=
570
-                       (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
571
+                       ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >=
572
+                        {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]} );
573
                4'b1_110: match2 =
574
-                       ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) !=
575
-                       (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
576
+                       (match_cond2_ct != dvr2);
577
        endcase
578
 
579
 //
580
@@ -1263,29 +1357,57 @@ always @(dmr1 or match2 or wp)
581
                2'b11: wp[2] = 1'b0;
582
        endcase
583
 
584
+
585
 //
586
 // Compare To What (Match Condition 3)
587
 //
588
 always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
589
        or dcpu_dat_lsu or dcpu_we_i)
590
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
591
-               3'b001: match_cond3_ct = id_pc;         // insn fetch EA
592
-               3'b010: match_cond3_ct = dcpu_adr_i;    // load EA
593
-               3'b011: match_cond3_ct = dcpu_adr_i;    // store EA
594
-               3'b100: match_cond3_ct = dcpu_dat_dc;   // load data
595
-               3'b101: match_cond3_ct = dcpu_dat_lsu;  // store data
596
-               3'b110: match_cond3_ct = dcpu_adr_i;    // load/store EA
597
-               default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
598
-       endcase
599
+               3'b001: match_cond3_tmp = id_pc;                // insn fetch EA
600
+               3'b010: match_cond3_tmp = dcpu_adr_i;   // load EA
601
+               3'b011: match_cond3_tmp = dcpu_adr_i;   // store EA
602
+               3'b100: match_cond3_tmp = dcpu_dat_dc;  // load data
603
+               3'b101: match_cond3_tmp = dcpu_dat_lsu; // store data
604
+               3'b110: match_cond3_tmp = dcpu_adr_i;   // load/store EA
605
+               default:match_cond3_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
606
+       endcase
607
+
608
+// Transparently handle 8/16/32 bit bus accesses (Match Condition 3)
609
+// For addresses, leave unchanged
610
+// for 32-bit data, leave unchanged
611
+// for 8- or 16-bit data, move the active byte lane(s) to the LSB position
612
+// This will allow the value to be compared to the LSB(s) of the DVR
613
+always @(match_cond3_tmp or dcr3 or dcpu_be_i)
614
+  case (dcr3[`OR1200_DU_DCR_CT])               // synopsys parallel_case
615
+    3'b100,
616
+    3'b101,
617
+    3'b111:  begin // We're comparing to data
618
+      case (dcpu_be_i)
619
+        4'b1000: match_cond3_ct = { {24{dcr3[`OR1200_DU_DCR_SC] & match_cond3_tmp[31]}}, match_cond3_tmp[31:24]};
620
+        4'b0100: match_cond3_ct = { {24{dcr3[`OR1200_DU_DCR_SC] & match_cond3_tmp[23]}}, match_cond3_tmp[23:16]};
621
+        4'b0010: match_cond3_ct = { {24{dcr3[`OR1200_DU_DCR_SC] & match_cond3_tmp[15]}}, match_cond3_tmp[15:8]};
622
+        4'b0001: match_cond3_ct = { {24{dcr3[`OR1200_DU_DCR_SC] & match_cond3_tmp[7] }}, match_cond3_tmp[7:0]};
623
+        4'b1100: match_cond3_ct = { {16{dcr3[`OR1200_DU_DCR_SC] & match_cond3_tmp[31]}}, match_cond3_tmp[31:16]};
624
+        4'b0011: match_cond3_ct = { {16{dcr3[`OR1200_DU_DCR_SC] & match_cond3_tmp[15]}}, match_cond3_tmp[15:0]};
625
+        default: match_cond3_ct = match_cond3_tmp;
626
+      endcase
627
+    end
628
+    default: match_cond3_ct = match_cond3_tmp;  // We're comparing an address
629
+  endcase
630
 
631
 //
632
 // When To Compare (Match Condition 3)
633
 //
634
-always @(dcr3 or dcpu_cycstb_i)
635
-       case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
636
+always @(dcr3 or dcpu_cycstb_i or dcpu_we_i)
637
+       case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
638
                3'b000: match_cond3_stb = 1'b0;         //comparison disabled
639
                3'b001: match_cond3_stb = 1'b1;         // insn fetch EA
640
-               default:match_cond3_stb = dcpu_cycstb_i; // any load/store
641
+               3'b010: match_cond3_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load addr
642
+               3'b011: match_cond3_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store addr
643
+               3'b100: match_cond3_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load val
644
+               3'b101: match_cond3_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store val
645
+               default: match_cond3_stb = dcpu_cycstb_i; // any load/store
646
        endcase
647
 
648
 //
649
@@ -1297,23 +1419,21 @@ always @(match_cond3_stb or dcr3 or dvr3
650
                4'b1_000,
651
                4'b1_111: match3 = 1'b0;
652
                4'b1_001: match3 =
653
-                       ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) ==
654
-                       (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
655
+                       (match_cond3_ct == dvr3);
656
                4'b1_010: match3 =
657
-                       ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <
658
-                       (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
659
+                       ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <
660
+                        {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]} );
661
                4'b1_011: match3 =
662
-                       ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <=
663
-                       (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
664
+                       ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <=
665
+                        {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]} );
666
                4'b1_100: match3 =
667
-                       ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >
668
-                       (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
669
+                       ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >
670
+                        {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]} );
671
                4'b1_101: match3 =
672
-                       ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >=
673
-                       (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
674
+                       ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >=
675
+                        {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]} );
676
                4'b1_110: match3 =
677
-                       ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) !=
678
-                       (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
679
+                       (match_cond3_ct != dvr3);
680
        endcase
681
 
682
 //
683
@@ -1327,29 +1447,57 @@ always @(dmr1 or match3 or wp)
684
                2'b11: wp[3] = 1'b0;
685
        endcase
686
 
687
+
688
 //
689
 // Compare To What (Match Condition 4)
690
 //
691
 always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
692
        or dcpu_dat_lsu or dcpu_we_i)
693
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
694
-               3'b001: match_cond4_ct = id_pc;         // insn fetch EA
695
-               3'b010: match_cond4_ct = dcpu_adr_i;    // load EA
696
-               3'b011: match_cond4_ct = dcpu_adr_i;    // store EA
697
-               3'b100: match_cond4_ct = dcpu_dat_dc;   // load data
698
-               3'b101: match_cond4_ct = dcpu_dat_lsu;  // store data
699
-               3'b110: match_cond4_ct = dcpu_adr_i;    // load/store EA
700
-               default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
701
-       endcase
702
+               3'b001: match_cond4_tmp = id_pc;                // insn fetch EA
703
+               3'b010: match_cond4_tmp = dcpu_adr_i;   // load EA
704
+               3'b011: match_cond4_tmp = dcpu_adr_i;   // store EA
705
+               3'b100: match_cond4_tmp = dcpu_dat_dc;  // load data
706
+               3'b101: match_cond4_tmp = dcpu_dat_lsu; // store data
707
+               3'b110: match_cond4_tmp = dcpu_adr_i;   // load/store EA
708
+               default:match_cond4_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
709
+       endcase
710
+
711
+// Transparently handle 8/16/32 bit bus accesses (Match Condition 4)
712
+// For addresses, leave unchanged
713
+// for 32-bit data, leave unchanged
714
+// for 8- or 16-bit data, move the active byte lane(s) to the LSB position
715
+// This will allow the value to be compared to the LSB(s) of the DVR
716
+always @(match_cond4_tmp or dcr4 or dcpu_be_i)
717
+  case (dcr4[`OR1200_DU_DCR_CT])               // synopsys parallel_case
718
+    3'b100,
719
+    3'b101,
720
+    3'b111:  begin // We're comparing to data
721
+      case (dcpu_be_i)
722
+        4'b1000: match_cond4_ct = { {24{dcr4[`OR1200_DU_DCR_SC] & match_cond4_tmp[31]}}, match_cond4_tmp[31:24]};
723
+        4'b0100: match_cond4_ct = { {24{dcr4[`OR1200_DU_DCR_SC] & match_cond4_tmp[23]}}, match_cond4_tmp[23:16]};
724
+        4'b0010: match_cond4_ct = { {24{dcr4[`OR1200_DU_DCR_SC] & match_cond4_tmp[15]}}, match_cond4_tmp[15:8]};
725
+        4'b0001: match_cond4_ct = { {24{dcr4[`OR1200_DU_DCR_SC] & match_cond4_tmp[7] }}, match_cond4_tmp[7:0]};
726
+        4'b1100: match_cond4_ct = { {16{dcr4[`OR1200_DU_DCR_SC] & match_cond4_tmp[31]}}, match_cond4_tmp[31:16]};
727
+        4'b0011: match_cond4_ct = { {16{dcr4[`OR1200_DU_DCR_SC] & match_cond4_tmp[15]}}, match_cond4_tmp[15:0]};
728
+        default: match_cond4_ct = match_cond4_tmp;
729
+      endcase
730
+    end
731
+    default: match_cond4_ct = match_cond4_tmp;  // We're comparing an address
732
+  endcase
733
 
734
 //
735
 // When To Compare (Match Condition 4)
736
 //
737
-always @(dcr4 or dcpu_cycstb_i)
738
-       case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
739
+always @(dcr4 or dcpu_cycstb_i or dcpu_we_i)
740
+       case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
741
                3'b000: match_cond4_stb = 1'b0;         //comparison disabled
742
                3'b001: match_cond4_stb = 1'b1;         // insn fetch EA
743
-               default:match_cond4_stb = dcpu_cycstb_i; // any load/store
744
+               3'b010: match_cond4_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load addr
745
+               3'b011: match_cond4_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store addr
746
+               3'b100: match_cond4_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load val
747
+               3'b101: match_cond4_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store val
748
+               default: match_cond4_stb = dcpu_cycstb_i; // any load/store
749
        endcase
750
 
751
 //
752
@@ -1361,23 +1509,21 @@ always @(match_cond4_stb or dcr4 or dvr4
753
                4'b1_000,
754
                4'b1_111: match4 = 1'b0;
755
                4'b1_001: match4 =
756
-                       ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) ==
757
-                       (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
758
+                       (match_cond4_ct == dvr4);
759
                4'b1_010: match4 =
760
-                       ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <
761
-                       (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
762
+                       ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <
763
+                        {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]} );
764
                4'b1_011: match4 =
765
-                       ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <=
766
-                       (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
767
+                       ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <=
768
+                        {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]} );
769
                4'b1_100: match4 =
770
-                       ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >
771
-                       (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
772
+                       ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >
773
+                        {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]} );
774
                4'b1_101: match4 =
775
-                       ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >=
776
-                       (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
777
+                       ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >=
778
+                        {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]} );
779
                4'b1_110: match4 =
780
-                       ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) !=
781
-                       (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
782
+                       (match_cond4_ct != dvr4);
783
        endcase
784
 
785
 //
786
@@ -1391,29 +1537,57 @@ always @(dmr1 or match4 or wp)
787
                2'b11: wp[4] = 1'b0;
788
        endcase
789
 
790
+
791
 //
792
 // Compare To What (Match Condition 5)
793
 //
794
 always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
795
        or dcpu_dat_lsu or dcpu_we_i)
796
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
797
-               3'b001: match_cond5_ct = id_pc;         // insn fetch EA
798
-               3'b010: match_cond5_ct = dcpu_adr_i;    // load EA
799
-               3'b011: match_cond5_ct = dcpu_adr_i;    // store EA
800
-               3'b100: match_cond5_ct = dcpu_dat_dc;   // load data
801
-               3'b101: match_cond5_ct = dcpu_dat_lsu;  // store data
802
-               3'b110: match_cond5_ct = dcpu_adr_i;    // load/store EA
803
-               default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
804
-       endcase
805
+               3'b001: match_cond5_tmp = id_pc;                // insn fetch EA
806
+               3'b010: match_cond5_tmp = dcpu_adr_i;   // load EA
807
+               3'b011: match_cond5_tmp = dcpu_adr_i;   // store EA
808
+               3'b100: match_cond5_tmp = dcpu_dat_dc;  // load data
809
+               3'b101: match_cond5_tmp = dcpu_dat_lsu; // store data
810
+               3'b110: match_cond5_tmp = dcpu_adr_i;   // load/store EA
811
+               default:match_cond5_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
812
+       endcase
813
+
814
+// Transparently handle 8/16/32 bit bus accesses (Match Condition 5)
815
+// For addresses, leave unchanged
816
+// for 32-bit data, leave unchanged
817
+// for 8- or 16-bit data, move the active byte lane(s) to the LSB position
818
+// This will allow the value to be compared to the LSB(s) of the DVR
819
+always @(match_cond5_tmp or dcr5 or dcpu_be_i)
820
+  case (dcr5[`OR1200_DU_DCR_CT])               // synopsys parallel_case
821
+    3'b100,
822
+    3'b101,
823
+    3'b111:  begin // We're comparing to data
824
+      case (dcpu_be_i)
825
+        4'b1000: match_cond5_ct = { {24{dcr5[`OR1200_DU_DCR_SC] & match_cond5_tmp[31]}}, match_cond5_tmp[31:24]};
826
+        4'b0100: match_cond5_ct = { {24{dcr5[`OR1200_DU_DCR_SC] & match_cond5_tmp[23]}}, match_cond5_tmp[23:16]};
827
+        4'b0010: match_cond5_ct = { {24{dcr5[`OR1200_DU_DCR_SC] & match_cond5_tmp[15]}}, match_cond5_tmp[15:8]};
828
+        4'b0001: match_cond5_ct = { {24{dcr5[`OR1200_DU_DCR_SC] & match_cond5_tmp[7] }}, match_cond5_tmp[7:0]};
829
+        4'b1100: match_cond5_ct = { {16{dcr5[`OR1200_DU_DCR_SC] & match_cond5_tmp[31]}}, match_cond5_tmp[31:16]};
830
+        4'b0011: match_cond5_ct = { {16{dcr5[`OR1200_DU_DCR_SC] & match_cond5_tmp[15]}}, match_cond5_tmp[15:0]};
831
+        default: match_cond5_ct = match_cond5_tmp;
832
+      endcase
833
+    end
834
+    default: match_cond5_ct = match_cond5_tmp;  // We're comparing an address
835
+  endcase
836
 
837
 //
838
 // When To Compare (Match Condition 5)
839
 //
840
-always @(dcr5 or dcpu_cycstb_i)
841
-       case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
842
+always @(dcr5 or dcpu_cycstb_i or dcpu_we_i)
843
+       case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
844
                3'b000: match_cond5_stb = 1'b0;         //comparison disabled
845
                3'b001: match_cond5_stb = 1'b1;         // insn fetch EA
846
-               default:match_cond5_stb = dcpu_cycstb_i; // any load/store
847
+               3'b010: match_cond5_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load addr
848
+               3'b011: match_cond5_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store addr
849
+               3'b100: match_cond5_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load val
850
+               3'b101: match_cond5_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store val
851
+               default: match_cond5_stb = dcpu_cycstb_i; // any load/store
852
        endcase
853
 
854
 //
855
@@ -1425,23 +1599,21 @@ always @(match_cond5_stb or dcr5 or dvr5
856
                4'b1_000,
857
                4'b1_111: match5 = 1'b0;
858
                4'b1_001: match5 =
859
-                       ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) ==
860
-                       (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
861
+                       (match_cond5_ct == dvr5);
862
                4'b1_010: match5 =
863
-                       ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <
864
-                       (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
865
+                       ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <
866
+                        {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]} );
867
                4'b1_011: match5 =
868
-                       ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <=
869
-                       (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
870
+                       ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <=
871
+                        {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]} );
872
                4'b1_100: match5 =
873
-                       ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >
874
-                       (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
875
+                       ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >
876
+                        {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]} );
877
                4'b1_101: match5 =
878
-                       ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >=
879
-                       (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
880
+                       ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >=
881
+                        {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]} );
882
                4'b1_110: match5 =
883
-                       ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) !=
884
-                       (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
885
+                       (match_cond5_ct != dvr5);
886
        endcase
887
 
888
 //
889
@@ -1455,29 +1627,57 @@ always @(dmr1 or match5 or wp)
890
                2'b11: wp[5] = 1'b0;
891
        endcase
892
 
893
+
894
 //
895
 // Compare To What (Match Condition 6)
896
 //
897
 always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
898
        or dcpu_dat_lsu or dcpu_we_i)
899
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
900
-               3'b001: match_cond6_ct = id_pc;         // insn fetch EA
901
-               3'b010: match_cond6_ct = dcpu_adr_i;    // load EA
902
-               3'b011: match_cond6_ct = dcpu_adr_i;    // store EA
903
-               3'b100: match_cond6_ct = dcpu_dat_dc;   // load data
904
-               3'b101: match_cond6_ct = dcpu_dat_lsu;  // store data
905
-               3'b110: match_cond6_ct = dcpu_adr_i;    // load/store EA
906
-               default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
907
-       endcase
908
+               3'b001: match_cond6_tmp = id_pc;                // insn fetch EA
909
+               3'b010: match_cond6_tmp = dcpu_adr_i;   // load EA
910
+               3'b011: match_cond6_tmp = dcpu_adr_i;   // store EA
911
+               3'b100: match_cond6_tmp = dcpu_dat_dc;  // load data
912
+               3'b101: match_cond6_tmp = dcpu_dat_lsu; // store data
913
+               3'b110: match_cond6_tmp = dcpu_adr_i;   // load/store EA
914
+               default:match_cond6_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
915
+       endcase
916
+
917
+// Transparently handle 8/16/32 bit bus accesses:
918
+// For addresses, leave unchanged
919
+// for 32-bit data, leave unchanged
920
+// for 8- or 16-bit data, move the active byte lane(s) to the LSB position
921
+// This will allow the value to be compared to the LSB(s) of the DVR
922
+always @(match_cond6_tmp or dcr6 or dcpu_be_i)
923
+  case (dcr6[`OR1200_DU_DCR_CT])               // synopsys parallel_case
924
+    3'b100,
925
+    3'b101,
926
+    3'b111:  begin // We're comparing to data
927
+      case (dcpu_be_i)
928
+        4'b1000: match_cond6_ct = { {24{dcr6[`OR1200_DU_DCR_SC] & match_cond6_tmp[31]}}, match_cond6_tmp[31:24]};
929
+        4'b0100: match_cond6_ct = { {24{dcr6[`OR1200_DU_DCR_SC] & match_cond6_tmp[23]}}, match_cond6_tmp[23:16]};
930
+        4'b0010: match_cond6_ct = { {24{dcr6[`OR1200_DU_DCR_SC] & match_cond6_tmp[15]}}, match_cond6_tmp[15:8]};
931
+        4'b0001: match_cond6_ct = { {24{dcr6[`OR1200_DU_DCR_SC] & match_cond6_tmp[7] }}, match_cond6_tmp[7:0]};
932
+        4'b1100: match_cond6_ct = { {16{dcr6[`OR1200_DU_DCR_SC] & match_cond6_tmp[31]}}, match_cond6_tmp[31:16]};
933
+        4'b0011: match_cond6_ct = { {16{dcr6[`OR1200_DU_DCR_SC] & match_cond6_tmp[15]}}, match_cond6_tmp[15:0]};
934
+        default: match_cond6_ct = match_cond6_tmp;
935
+      endcase
936
+    end
937
+    default: match_cond6_ct = match_cond6_tmp;  // We're comparing an address
938
+  endcase
939
 
940
 //
941
 // When To Compare (Match Condition 6)
942
 //
943
-always @(dcr6 or dcpu_cycstb_i)
944
-       case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
945
+always @(dcr6 or dcpu_cycstb_i or dcpu_we_i)
946
+       case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
947
                3'b000: match_cond6_stb = 1'b0;         //comparison disabled
948
                3'b001: match_cond6_stb = 1'b1;         // insn fetch EA
949
-               default:match_cond6_stb = dcpu_cycstb_i; // any load/store
950
+               3'b010: match_cond6_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load addr
951
+               3'b011: match_cond6_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store addr
952
+               3'b100: match_cond6_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load val
953
+               3'b101: match_cond6_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store val
954
+               default: match_cond6_stb = dcpu_cycstb_i; // any load/store
955
        endcase
956
 
957
 //
958
@@ -1489,23 +1689,21 @@ always @(match_cond6_stb or dcr6 or dvr6
959
                4'b1_000,
960
                4'b1_111: match6 = 1'b0;
961
                4'b1_001: match6 =
962
-                       ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) ==
963
-                       (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
964
+                       (match_cond6_ct == dvr6);
965
                4'b1_010: match6 =
966
-                       ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <
967
-                       (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
968
+                       ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <
969
+                        {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]} );
970
                4'b1_011: match6 =
971
-                       ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <=
972
-                       (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
973
+                       ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <=
974
+                        {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]} );
975
                4'b1_100: match6 =
976
-                       ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >
977
-                       (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
978
+                       ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >
979
+                        {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]} );
980
                4'b1_101: match6 =
981
-                       ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >=
982
-                       (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
983
+                       ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >=
984
+                        {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]} );
985
                4'b1_110: match6 =
986
-                       ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) !=
987
-                       (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
988
+                       (match_cond6_ct != dvr6);
989
        endcase
990
 
991
 //
992
@@ -1525,27 +1723,58 @@ always @(dmr1 or match6 or wp)
993
 always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
994
        or dcpu_dat_lsu or dcpu_we_i)
995
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
996
-               3'b001: match_cond7_ct = id_pc;         // insn fetch EA
997
-               3'b010: match_cond7_ct = dcpu_adr_i;    // load EA
998
-               3'b011: match_cond7_ct = dcpu_adr_i;    // store EA
999
-               3'b100: match_cond7_ct = dcpu_dat_dc;   // load data
1000
-               3'b101: match_cond7_ct = dcpu_dat_lsu;  // store data
1001
-               3'b110: match_cond7_ct = dcpu_adr_i;    // load/store EA
1002
-               default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1003
-       endcase
1004
+               3'b001: match_cond7_tmp = id_pc;                // insn fetch EA -- *** use spr_dat_npc?? ***
1005
+               3'b010: match_cond7_tmp = dcpu_adr_i;   // load EA
1006
+               3'b011: match_cond7_tmp = dcpu_adr_i;   // store EA
1007
+               3'b100: match_cond7_tmp = dcpu_dat_dc;  // load data
1008
+               3'b101: match_cond7_tmp = dcpu_dat_lsu; // store data
1009
+               3'b110: match_cond7_tmp = dcpu_adr_i;   // load/store EA
1010
+               default:match_cond7_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1011
+       endcase
1012
+
1013
+// Transparently handle 8/16/32 bit bus accesses:
1014
+// For addresses, leave unchanged
1015
+// for 32-bit data, leave unchanged
1016
+// for 8- or 16-bit data, move the active byte lane(s) to the LSB position
1017
+// This will allow the value to be compared to the LSB(s) of the DVR.
1018
+// If we're doing a signed compare (DCR_SC is set), we sign-extend.  If not, zero-pad.
1019
+// This means that for a signed comparison, the DVR must ALWAYS be a 32-bit signed
1020
+// number, even if only doing on 8-bit compare!
1021
+always @(match_cond7_tmp or dcr7 or dcpu_be_i)
1022
+  case (dcr7[`OR1200_DU_DCR_CT])               // synopsys parallel_case
1023
+    3'b100,
1024
+    3'b101,
1025
+    3'b111:  begin // We're comparing to data
1026
+      case (dcpu_be_i)
1027
+        4'b1000: match_cond7_ct = { {24{dcr7[`OR1200_DU_DCR_SC] & match_cond7_tmp[31]}}, match_cond7_tmp[31:24]};
1028
+        4'b0100: match_cond7_ct = { {24{dcr7[`OR1200_DU_DCR_SC] & match_cond7_tmp[23]}}, match_cond7_tmp[23:16]};
1029
+        4'b0010: match_cond7_ct = { {24{dcr7[`OR1200_DU_DCR_SC] & match_cond7_tmp[15]}}, match_cond7_tmp[15:8]};
1030
+        4'b0001: match_cond7_ct = { {24{dcr7[`OR1200_DU_DCR_SC] & match_cond7_tmp[7] }}, match_cond7_tmp[7:0]};
1031
+        4'b1100: match_cond7_ct = { {16{dcr7[`OR1200_DU_DCR_SC] & match_cond7_tmp[31]}}, match_cond7_tmp[31:16]};
1032
+        4'b0011: match_cond7_ct = { {16{dcr7[`OR1200_DU_DCR_SC] & match_cond7_tmp[15]}}, match_cond7_tmp[15:0]};
1033
+        default: match_cond7_ct = match_cond7_tmp;
1034
+      endcase
1035
+    end
1036
+    default: match_cond7_ct = match_cond7_tmp;  // We're comparing an address
1037
+  endcase
1038
 
1039
 //
1040
 // When To Compare (Match Condition 7)
1041
 //
1042
-always @(dcr7 or dcpu_cycstb_i)
1043
+always @(dcr7 or dcpu_cycstb_i or dcpu_we_i)
1044
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1045
                3'b000: match_cond7_stb = 1'b0;         //comparison disabled
1046
                3'b001: match_cond7_stb = 1'b1;         // insn fetch EA
1047
-               default:match_cond7_stb = dcpu_cycstb_i; // any load/store
1048
+               3'b010: match_cond7_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load addr
1049
+               3'b011: match_cond7_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store addr
1050
+               3'b100: match_cond7_stb = (dcpu_cycstb_i & (~dcpu_we_i));  // data load val
1051
+               3'b101: match_cond7_stb = (dcpu_cycstb_i & dcpu_we_i);     // data store val
1052
+               default: match_cond7_stb = dcpu_cycstb_i; // any load/store
1053
        endcase
1054
 
1055
 //
1056
 // Match Condition 7
1057
+// To do a signed comparison, we invert the MSB then do an unsigned comparison.
1058
 //
1059
 always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
1060
        casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
1061
@@ -1553,23 +1782,21 @@ always @(match_cond7_stb or dcr7 or dvr7
1062
                4'b1_000,
1063
                4'b1_111: match7 = 1'b0;
1064
                4'b1_001: match7 =
1065
-                       ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) ==
1066
-                       (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1067
+                       (match_cond7_ct == dvr7);
1068
                4'b1_010: match7 =
1069
-                       ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <
1070
-                       (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1071
+                       ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <
1072
+                        {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]} );
1073
                4'b1_011: match7 =
1074
-                       ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <=
1075
-                       (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1076
+                       ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <=
1077
+                        {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]} );
1078
                4'b1_100: match7 =
1079
-                       ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >
1080
-                       (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1081
+                       ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >
1082
+                        {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]} );
1083
                4'b1_101: match7 =
1084
-                       ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >=
1085
-                       (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1086
+                       ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >=
1087
+                        {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]} );
1088
                4'b1_110: match7 =
1089
-                       ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) !=
1090
-                       (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1091
+                       (match_cond7_ct != dvr7);
1092
        endcase
1093
 
1094
 //
1095
@@ -1586,11 +1813,19 @@ always @(dmr1 or match7 or wp)
1096
 //
1097
 // Increment Watchpoint Counter 0
1098
 //
1099
-always @(wp or dmr2)
1100
-       if (dmr2[`OR1200_DU_DMR2_WCE0])
1101
-               incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
1102
-       else
1103
-               incr_wpcntr0 = 1'b0;
1104
+
1105
+// A watchpoint may hold it's wp bit high for >1 clock while ex_freeze
1106
+// is high, but drop it when ex_freeze is low.  So, increment on wp will over-increment,
1107
+// but AND'ing with ex_freeze will never increment.  Solution:  hold the wp when set,
1108
+// inc the counter only when ex_freeze is false.
1109
+always @ (posedge clk)
1110
+begin
1111
+  if(rst) incr_wpcntr0_latched <= 1'b0;
1112
+  else if(ex_freeze & (|(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]))) incr_wpcntr0_latched <= 1'b1;
1113
+  else if(~ex_freeze) incr_wpcntr0_latched <= 1'b0;
1114
+end
1115
+
1116
+assign incr_wpcntr0 = dmr2[`OR1200_DU_DMR2_WCE0] & (~ex_freeze & (incr_wpcntr0_latched | (|(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]))));
1117
 
1118
 //
1119
 // Match Condition Watchpoint Counter 0
1120
@@ -1601,15 +1836,35 @@ always @(dwcr0)
1121
        else
1122
                wpcntr0_match = 1'b0;
1123
 
1124
+//
1125
+// Breakpoint Triggering - Counter 1
1126
+// While the standard watchpoint hardware won't give a match for more than one
1127
+// clock cycle, the counters will give a constant match.  This will be registered,
1128
+// causing a second trap condition after a continue.  To fix this, just pulse the
1129
+// break output high for 1 clock cycle, and don't do it again until the match
1130
+// condition has been negated for at least 1 clock cycle.  The new break output
1131
+// is called wpcntrX_oneshot.
1132
+//
1133
+always @ (posedge clk)
1134
+begin
1135
+       if(wpcntr0_match & wpcntr0_armed) wpcntr0_oneshot = 1'b1;
1136
+       else wpcntr0_oneshot = 1'b0;
1137
+end
1138
+
1139
+always @(posedge clk)
1140
+begin
1141
+       if(wpcntr0_match) wpcntr0_armed = 1'b0;
1142
+       else wpcntr0_armed = 1'b1;
1143
+end
1144
 
1145
 //
1146
-// Watchpoint 8
1147
+// Watchpoint 8 (Counter 0)
1148
 //
1149
-always @(dmr1 or wpcntr0_match or wp)
1150
+always @(dmr1 or wpcntr0_oneshot or wp)
1151
        case (dmr1[`OR1200_DU_DMR1_CW8])
1152
-               2'b00: wp[8] = wpcntr0_match;
1153
-               2'b01: wp[8] = wpcntr0_match & wp[7];
1154
-               2'b10: wp[8] = wpcntr0_match | wp[7];
1155
+               2'b00: wp[8] = wpcntr0_oneshot;
1156
+               2'b01: wp[8] = wpcntr0_oneshot & wp[3];
1157
+               2'b10: wp[8] = wpcntr0_oneshot | wp[3];
1158
                2'b11: wp[8] = 1'b0;
1159
        endcase
1160
 
1161
@@ -1617,11 +1872,18 @@ always @(dmr1 or wpcntr0_match or wp)
1162
 //
1163
 // Increment Watchpoint Counter 1
1164
 //
1165
-always @(wp or dmr2)
1166
-       if (dmr2[`OR1200_DU_DMR2_WCE1])
1167
-               incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
1168
-       else
1169
-               incr_wpcntr1 = 1'b0;
1170
+// A watchpoint may hold it's wp bit high for >1 clock while ex_freeze
1171
+// is high, but drop it when ex_freeze is low.  So, increment on wp will over-increment,
1172
+// but AND'ing with ex_freeze will never increment.  Solution:  hold the wp when set,
1173
+// inc the counter only when ex_freeze is false.
1174
+always @ (posedge clk)
1175
+begin
1176
+  if(rst) incr_wpcntr1_latched <= 1'b0;
1177
+  else if(ex_freeze & (|(wp & dmr2[`OR1200_DU_DMR2_AWTC]))) incr_wpcntr1_latched <= 1'b1;
1178
+  else if(~ex_freeze) incr_wpcntr1_latched <= 1'b0;
1179
+end
1180
+
1181
+assign incr_wpcntr1 = dmr2[`OR1200_DU_DMR2_WCE1] & (~ex_freeze & (incr_wpcntr1_latched | (|(wp & dmr2[`OR1200_DU_DMR2_AWTC]))));
1182
 
1183
 //
1184
 // Match Condition Watchpoint Counter 1
1185
@@ -1633,36 +1895,70 @@ always @(dwcr1)
1186
                wpcntr1_match = 1'b0;
1187
 
1188
 //
1189
-// Watchpoint 9
1190
-//
1191
-always @(dmr1 or wpcntr1_match or wp)
1192
-       case (dmr1[`OR1200_DU_DMR1_CW9])
1193
-               2'b00: wp[9] = wpcntr1_match;
1194
-               2'b01: wp[9] = wpcntr1_match & wp[8];
1195
-               2'b10: wp[9] = wpcntr1_match | wp[8];
1196
-               2'b11: wp[9] = 1'b0;
1197
-       endcase
1198
+// Breakpoint Triggering - Counter 1
1199
+// While the standard watchpoint hardware won't give a match for more than one
1200
+// clock cycle, the counters will give a constant match.  This will be registered,
1201
+// causing a second trap condition after a continue.  To fix this, just pulse the
1202
+// break output high for 1 clock cycle, and don't do it again until the match
1203
+// condition has been negated for at least 1 clock cycle.  The new break output
1204
+// is called wpcntrX_oneshot.
1205
+//
1206
+always @ (posedge clk)
1207
+begin
1208
+       if(wpcntr1_match & wpcntr1_armed) wpcntr1_oneshot = 1'b1;
1209
+       else wpcntr1_oneshot = 1'b0;
1210
+end
1211
+
1212
+always @(posedge clk)
1213
+begin
1214
+       if(wpcntr1_match) wpcntr1_armed = 1'b0;
1215
+       else wpcntr1_armed = 1'b1;
1216
+end
1217
 
1218
 //
1219
-// Watchpoint 10
1220
+// Watchpoint 9 (Counter 1)
1221
 //
1222
-always @(dmr1 or dbg_ewt_i or wp)
1223
-       case (dmr1[`OR1200_DU_DMR1_CW10])
1224
-               2'b00: wp[10] = dbg_ewt_i;
1225
-               2'b01: wp[10] = dbg_ewt_i & wp[9];
1226
-               2'b10: wp[10] = dbg_ewt_i | wp[9];
1227
-               2'b11: wp[10] = 1'b0;
1228
+always @(dmr1 or wpcntr1_oneshot or wp)
1229
+       case (dmr1[`OR1200_DU_DMR1_CW9])
1230
+               2'b00: wp[9] = wpcntr1_oneshot;
1231
+               2'b01: wp[9] = wpcntr1_oneshot & wp[7];
1232
+               2'b10: wp[9] = wpcntr1_oneshot | wp[7];
1233
+               2'b11: wp[9] = 1'b0;
1234
        endcase
1235
 
1236
 `endif
1237
 
1238
+
1239
 //
1240
 // Watchpoints can cause trap exception
1241
 //
1242
 `ifdef OR1200_DU_HWBKPTS
1243
-assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]);
1244
+
1245
+// We must hold the du_hwbkpt signal high until it's noticed by the execution unit,
1246
+// which means until the 'freeze' signal goes inactive.
1247
+
1248
+always @ (posedge clk)
1249
+begin
1250
+  if(rst) du_hwbkpt_latched <= 1'b0;
1251
+  else if(ex_freeze & (|(wp & dmr2[`OR1200_DU_DMR2_WGB]))) du_hwbkpt_latched <= 1'b1;
1252
+  else if(~ex_freeze) du_hwbkpt_latched <= 1'b0;
1253
+end
1254
+
1255
+assign du_hwbkpt = du_hwbkpt_latched | (|(wp & dmr2[`OR1200_DU_DMR2_WGB]));
1256
+
1257
+  `ifdef OR1200_DU_DMR2
1258
+// Spec doesn't state what resets the WGB bits in DMR2.
1259
+// This implementation resets on any write to the DMR2.
1260
+always @ (posedge clk)
1261
+begin
1262
+       if(rst | (dmr2_sel & spr_write)) wp_latched <= 10'h000;
1263
+       else if((|(wp & dmr2[`OR1200_DU_DMR2_WGB]))/*du_hwbkpt*/ & !(|wp_latched)) wp_latched <= (wp & dmr2[`OR1200_DU_DMR2_WGB]);
1264
+end
1265
+  `endif
1266
+
1267
 `else
1268
 assign du_hwbkpt = 1'b0;
1269
+assign wp_latched = 10'h000;
1270
 `endif
1271
 
1272
 `ifdef OR1200_DU_TB_IMPLEMENTED

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